kernel/linux.git/drivers/clk/qcom/gdsc.c, branch linux-7.0.y

clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains

2026-05-23T11:09:15+00:00

[ Upstream commit 16ba98dace9e7cfe25ad8a314e34befacd91f86f ] Some pm subdomains may be left in added to a parent domain state, if gdsc_add_subdomain_list() function fails in the middle and bails from a GDSC power domain controller registration out. Fixes: b489235b4dc0 ("clk: qcom: Support attaching GDSCs to multiple parents") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20260328012619.832770-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin

clk: qcom: gdsc: Update the status poll timeout for GDSC

2025-03-13T21:39:06+00:00

During the GDSC FSM state, the GDSC hardware waits for an ACK from the respective subsystem core. In some scenarios, this ACK can be delayed. To handle such delays, increase the GDSC status poll timeout from 1500us to 2000us as per the design recommendation. Signed-off-by: Taniya Das Reviewed-by: Imran Shaik Tested-by: Imran Shaik # on QCS8300 Link: https://lore.kernel.org/r/20250214-gdsc_fixes-v1-2-73e56d68a80f@quicinc.com Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Set retain_ff before moving to HW CTRL

2025-03-13T21:39:06+00:00

Enable the retain_ff_enable bit of GDSCR only if the GDSC is already ON. Once the GDSCR moves to HW control, SW no longer can determine the state of the GDSCR and setting the retain_ff bit could destroy all the register contents we intended to save. Therefore, move the retain_ff configuration before switching the GDSC to HW trigger mode. Cc: stable@vger.kernel.org Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Taniya Das Reviewed-by: Imran Shaik Tested-by: Imran Shaik # on QCS8300 Link: https://lore.kernel.org/r/20250214-gdsc_fixes-v1-1-73e56d68a80f@quicinc.com Signed-off-by: Bjorn Andersson

clk: qcom: Support attaching GDSCs to multiple parents

2025-02-08T05:20:55+00:00

When a clock-controller lists multiple power-domains we need make each GDSC a subdomain of each of the clock-controller's listed power-domains. GDSCs without an explicitly defined parent should be a subdomain of each of the clock-controller's listed power-domains. GDSCs with an explicitly defined parent should attach only to the parent GDSC and not the listed power-domains. Any votes will trickle through the hierarchy up to the external power-domains. ======================================== :: arch/arm64/boot/dts/example.dtsi :: ======================================== clockcc: clock-controller@0 { compat ="qcom,example-clockcc"; power-domains = <&pd_a, &pd_b>; } ======================================== :: drivers/clk/qcom/example-clockcc.c :: ======================================== static struct gdsc parent_gdsc = { .pd = { .name = "parent_gdsc", }, }; static struct gdsc child0_gdsc = { .pd = { .name = "child0_gdsc", }, .parent = &parent_gdsc.pd, }; static struct gdsc child1_gdsc = { .pd = { .name = "child1_gdsc", }, .parent = &parent_gdsc.pd, }; ======================================== :: power-subdomains :: ======================================== pm-domain::pd_a └── pm-subdomain::clockcc::parent_gdsc ├── pm-subdomain::clockcc::child0_gdsc └── pm-subdomain::clockcc::child1_gdsc pm-domain::pd_b └── pm-subdomain::clockcc::parent_gdsc ├── pm-subdomain::clockcc::child1_gdsc └── pm-subdomain::clockcc::child2_gdsc The performance states will percolate through the pm-domain hierarchy to the domains that handle the relevant states. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-4-13f2bb656dad@linaro.org Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Capture pm_genpd_add_subdomain result code

2025-02-08T05:20:55+00:00

Adding a new clause to this if/else I noticed the existing usage of pm_genpd_add_subdomain() wasn't capturing and returning the result code. pm_genpd_add_subdomain() returns an int and can fail. Capture that result code and throw it up the call stack if something goes wrong. Fixes: 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-2-13f2bb656dad@linaro.org Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Release pm subdomains in reverse add order

2025-02-08T05:20:55+00:00

gdsc_unregister() should release subdomains in the reverse order to the order in which those subdomains were added. I've made this patch a standalone patch because it facilitates a subsequent fix to stable. Fixes: 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-1-13f2bb656dad@linaro.org Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode

2024-07-09T10:59:58+00:00

Some GDSC client drivers require the GDSC mode to be switched dynamically to HW mode at runtime to gain the power benefits. Typically such client drivers require the GDSC to be brought up in SW mode initially to enable the required dependent clocks and configure the hardware to proper state. Once initial hardware set up is done, they switch the GDSC to HW mode to save power. At the end of usecase, they switch the GDSC back to SW mode and disable the GDSC. Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and get_hwmode_dev callbacks for GDSC's whose respective client drivers require the GDSC mode to be switched dynamically at runtime using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona Signed-off-by: Abel Vesa Reviewed-by: Bryan O'Donoghue Reviewed-by: Taniya Das Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240624044809.17751-4-quic_jkona@quicinc.com Signed-off-by: Ulf Hansson

clk: qcom: gdsc: treat optional supplies as optional

2024-04-03T03:47:07+00:00

Since commit deebc79b28d6 ("clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc") the GDSC supply must be treated as optional to avoid warnings like: gpu_cc-sc8280xp 3d90000.clock-controller: supply vdd-gfx not found, using dummy regulator on SC8280XP. Fortunately, the driver is already prepared to handle this by checking that the regulator pointer is non-NULL before use. This also avoids triggering a potential deadlock on SC8280XP even if the underlying issue still remains for the derivative platforms like SA8295P that actually use the supply. Fixes: deebc79b28d6 ("clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc") Link: https://lore.kernel.org/lkml/Zf25Sv2x9WaCFuIH@hovoldconsulting.com/ Signed-off-by: Johan Hovold Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240325085835.26158-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Enable supply reglator in GPU GX handler

2024-01-30T20:48:01+00:00

The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-2-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson

clk: qcom: gdsc: Support 'synced_poweroff' genpd flag

2023-01-10T17:07:10+00:00

Add support for the newly added 'synced_poweroff' genpd flag. This allows some clients (like adreno gpu driver) to request gdsc driver to ensure a votable gdsc (like gpucc cx gdsc) has collapsed at hardware. Signed-off-by: Akhil P Oommen Reviewed-by: Ulf Hansson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230102161757.v5.2.Ic128c1df50b7fc9a6b919932a3b41a799b5ed5e8@changeid