kernel/linux.git/drivers/clk/qcom/gcc-sm8750.c, branch v7.0-rc6Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v7.0-rc62026-01-07T15:12:00+00:00clk: qcom: gcc-sm8750: Update the SDCC RCGs to use shared_floor_ops2026-01-07T15:12:00+00:00Jagadeesh Konajagadeesh.kona@oss.qualcomm.com2025-11-27T17:57:37+00:00urn:sha1:a7231d4aa084e485394f9214ec9bcb2d1f65dde9
Use shared_floor_ops for the SDCC RCGs so the RCG is safely parked
during disable and the new parent configuration is programmed in
hardware only when the new parent is enabled, avoiding cases where
the RCG configuration fails to update.
Fixes: 3267c774f3ff ("clk: qcom: Add support for GCC on SM8750")
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251127-sdcc_shared_floor_ops-v2-2-473afc86589c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: gcc-sm8750: Add a new frequency for sdcc2 clock2025-10-22T21:39:07+00:00Taniya Dastaniya.das@oss.qualcomm.com2025-09-23T18:38:30+00:00urn:sha1:393f7834cd2b1eaf4a9eff2701e706e73e660dd7
The SD card support requires a 37.5MHz clock; add it to the frequency
list for the storage SW driver to be able to request for the frequency.
Fixes: 3267c774f3ff ("clk: qcom: Add support for GCC on SM8750")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250924-sm8750_gcc_sdcc2_frequency-v1-1-541fd321125f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/87502025-05-18T00:28:40+00:00Taniya Dasquic_tdas@quicinc.com2025-04-14T09:00:40+00:00urn:sha1:da94a81ea6c6f1cd2f389c5631e33c145ac7b35b
Update the force mem core bit for UFS AXI clock to force the core on
signal to remain active during halt state of the clk. If force mem
core bit of the clock is not set, the memories of the subsystem will
not retain the logic across power states. This is required for the MCQ
feature of the UFS driver.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250414-gcc_ufs_mem_core-v1-1-67b5529b9b5d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
clk: qcom: Add support for GCC on SM87502025-01-06T16:29:27+00:00Taniya Dasquic_tdas@quicinc.com2024-12-04T19:37:18+00:00urn:sha1:3267c774f3ff61fc945a7531b2ae6784c37cd14f
Add support for GCC for SM8750 platform.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-6-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>