<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/clk/qcom/common.h, branch linux-5.9.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2019-08-08T15:20:01+00:00</updated>
<entry>
<title>clk: qcom: define probe by index API as common API</title>
<updated>2019-08-08T15:20:01+00:00</updated>
<author>
<name>Govind Singh</name>
<email>govinds@codeaurora.org</email>
</author>
<published>2019-07-26T09:23:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=75e0a1e301913b2b5627a69818f2521f48e6be07'/>
<id>urn:sha1:75e0a1e301913b2b5627a69818f2521f48e6be07</id>
<content type='text'>
Extend the probe by index API in common code to be used
by other qcom clock controller.

Signed-off-by: Govind Singh &lt;govinds@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Make common clk_hw registrations</title>
<updated>2019-02-22T08:06:57+00:00</updated>
<author>
<name>Jeffrey Hugo</name>
<email>jhugo@codeaurora.org</email>
</author>
<published>2019-02-10T20:14:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=760be6586fbcc0a5a3b7892e3fe664a3f0530631'/>
<id>urn:sha1:760be6586fbcc0a5a3b7892e3fe664a3f0530631</id>
<content type='text'>
Several clock controller drivers define a list of clk_hw devices, and then
register those devices in probe() before using common code to process the
rest of initialization.  Extend the common code to accept a list of clk_hw
devices to process, thus eliminating many duplicate implementations.

Signed-off-by: Jeffrey Hugo &lt;jhugo@codeaurora.org&gt;
Suggested-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Reviewed-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Tested-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Update SPDX headers for common files</title>
<updated>2018-07-25T16:23:33+00:00</updated>
<author>
<name>Taniya Das</name>
<email>tdas@codeaurora.org</email>
</author>
<published>2018-07-16T05:54:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f9419783a6b45a7198ea22f2997cf1a85fda8458'/>
<id>urn:sha1:f9419783a6b45a7198ea22f2997cf1a85fda8458</id>
<content type='text'>
SPDX headers updated for common/branch/pll/regmap files.

Signed-off-by: Taniya Das &lt;tdas@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: add parent map for regmap mux</title>
<updated>2017-12-22T00:03:22+00:00</updated>
<author>
<name>Abhishek Sahu</name>
<email>absahu@codeaurora.org</email>
</author>
<published>2017-12-13T14:25:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=df964016490b2cf630b1b926a1d5c610833aaa84'/>
<id>urn:sha1:df964016490b2cf630b1b926a1d5c610833aaa84</id>
<content type='text'>
Currently the driver assumes the register configuration value
is identical to its index in the parent map. This patch adds
the parent map field in regmap mux clock node which contains
the mapping of parent index with actual register configuration
value. If regmap node contains this parent map then the
configuration value will be taken from this
parent map instead of simply writing the index value.

Signed-off-by: Abhishek Sahu &lt;absahu@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Add rcg ops to return floor value closest to the requested rate</title>
<updated>2016-11-23T19:00:05+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2016-11-21T06:37:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=081ba80206d6b53d45ee31bc6c90871e8cfbc117'/>
<id>urn:sha1:081ba80206d6b53d45ee31bc6c90871e8cfbc117</id>
<content type='text'>
The default behaviour with clk_rcg2_ops is for the
clk_round_rate()/clk_set_rate() to return/set a ceil clock
rate closest to the requested rate by looking up the corresponding
frequency table.
However, we do have some instances (mainly sdcc on various platforms)
of clients expecting a clk_set_rate() to set a floor value instead.
Add a new clk_rcg2_floor_ops to handle this for such specific
rcg instances

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Ritesh Harjani &lt;riteshh@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Enable FSM mode for votable alpha PLLs</title>
<updated>2016-11-02T01:39:17+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2016-09-29T08:35:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=400d9fda39bc8e16412103796040aef484fe7f5d'/>
<id>urn:sha1:400d9fda39bc8e16412103796040aef484fe7f5d</id>
<content type='text'>
The votable alpha PLLs need to have the fsm mode enabled as part
of the initialization. The sequence seems to be the same as used
by clk-pll, so move the function which does this into a common
place and reuse it for the clk-alpha-pll

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Taniya Das &lt;tdas@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: common: Add API to register board clocks backwards compatibly</title>
<updated>2015-11-16T19:07:06+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-10-27T00:11:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ee15faffef11309219aa87a24efc86f6dd13f7cb'/>
<id>urn:sha1:ee15faffef11309219aa87a24efc86f6dd13f7cb</id>
<content type='text'>
We want to put the XO board clocks into the dt files, but we also
need to be backwards compatible with an older dtb. Add an API to
the common code to do this. This also makes a place for us to
handle the case when the RPM clock driver is enabled and we don't
want to register the fixed factor clock.

Cc: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Drop calls to qcom_cc_remove()</title>
<updated>2015-10-09T06:53:01+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-10-08T07:11:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9bc432cb242b0edff81e3ab83ba11c327cd4dd93'/>
<id>urn:sha1:9bc432cb242b0edff81e3ab83ba11c327cd4dd93</id>
<content type='text'>
Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.

Cc: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: gdsc: Prepare common clk probe to register gdscs</title>
<updated>2015-09-16T22:22:37+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2015-08-06T10:37:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5e5cc241e9c448d1f6e5fdef843ab018a9947d5c'/>
<id>urn:sha1:5e5cc241e9c448d1f6e5fdef843ab018a9947d5c</id>
<content type='text'>
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Introduce parent_map tables</title>
<updated>2015-03-23T23:09:19+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>georgi.djakov@linaro.org</email>
</author>
<published>2015-03-20T16:30:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=293d2e97b37f545bb36aef78cd549d9e6cd66e7f'/>
<id>urn:sha1:293d2e97b37f545bb36aef78cd549d9e6cd66e7f</id>
<content type='text'>
In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.

This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
 - Define a parent_map struct to map the relations between PLL source index
 and register configuration value.
 - Add a qcom_find_src_index() function for finding the index of a clock
 matching the specific PLL configuration.
 - Update the {set,get}_parent RCG functions use the newly introduced
 parent_map struct.
 - Convert all existing drivers to the new parent_map tables.

Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
