kernel/linux.git/drivers/clk/qcom/Kconfig, branch linux-4.16.y

Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-next

2018-01-27T00:41:58+00:00

* clk-iproc: clk: iproc: Minor tidy up of iproc pll data structures clk: iproc: Allow plls to do minor rate changes without reset clk: iproc: Fix error in the pll post divider rate calculation clk: iproc: Allow iproc pll to runtime calculate vco parameters * clk-mvebu: clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO() * clk-qcom-a53: clk: qcom: Add APCS clock controller support clk: qcom: Add regmap mux-div clocks support clk: qcom: Add A53 PLL support

clk: qcom: Add APCS clock controller support

2018-01-02T18:00:25+00:00

Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson Tested-by: Amit Kucheria [sboyd@codeaurora.org: Include rcg header for parent_map, drop multiple unneeded includes, add COMPILE_TEST to APCS depends, made tristate/modular] Signed-off-by: Stephen Boyd

clk: qcom: Add A53 PLL support

2018-01-02T18:00:24+00:00

The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson Tested-by: Amit Kucheria [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: Stephen Boyd

clk: qcom: Add spmi_pmic clock divider support

2017-12-07T06:30:30+00:00

Clkdiv module provides a clock output on the PMIC with CXO as the source. This clock can be routed through PMIC GPIOs. Add a device driver to configure this clkdiv module. Signed-off-by: Tirupathi Reddy [sboyd: Simplified code and moved to devm clk provider APIs] Signed-off-by: Stephen Boyd

clk: qcom: Add ipq8074 Global Clock Controller support

2017-06-20T00:29:41+00:00

This patch adds support for the global clock controller found on the ipq8074 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Abhishek Sahu Signed-off-by: Varadarajan Narayanan Signed-off-by: Stephen Boyd

Merge branch 'clk-qcom-rpm' into clk-next

2016-11-11T00:50:16+00:00

* clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks

clk: qcom: Add support for RPM Clocks

2016-11-11T00:46:56+00:00

This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by: Georgi Djakov Acked-by: Rob Herring Signed-off-by: Stephen Boyd

clk: qcom: Add support for SMD-RPM Clocks

2016-11-11T00:37:55+00:00

This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Signed-off-by: Georgi Djakov Acked-by: Rob Herring [sboyd@codeaurora.org: Remove useless braces for single line if] Signed-off-by: Stephen Boyd

clk: qcom: Add support for msm8994 global clock controller

2016-11-10T23:45:42+00:00

The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by: Bastian Köcher [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by: Jeremy McNicoll [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by: Stephen Boyd

clk: qcom: select GDSC for msm8996 gcc and mmcc

2016-08-25T19:51:17+00:00

This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: Srinivas Kandagatla Fixes: 52111672f791 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd