kernel/linux.git/drivers/clk/mstar, branch v6.12.80

clk: mstar: msc313 cpupll clk driver

2022-10-27T18:44:27+00:00

Add a driver for the CPU pll/ARM pll/MIPS pll that is present in MStar SoCs. Currently there is no documentation for this block so it's possible this driver isn't entirely correct. Only tested on the version of this IP in the MStar/SigmaStar ARMv7 SoCs. Signed-off-by: Daniel Palmer Co-developed-by: Willy Tarreau Signed-off-by: Willy Tarreau Signed-off-by: Romain Perier Link: https://lore.kernel.org/r/20221022133404.3832-2-romain.perier@gmail.com Signed-off-by: Stephen Boyd

clk: mstar: msc313-mpll: Fix format specifier

2021-02-16T20:52:28+00:00

The output dividers are unsigned int so the format specifier should have been %u not %d. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20210215115710.3762276-2-daniel@0x0f.com Signed-off-by: Stephen Boyd

clk: mstar: Allow MStar clk drivers to be compile tested

2021-02-16T20:52:21+00:00

Allow COMPILE_TEST to also build the MStar clk drivers instead of only building them when ARCH_MSTARV7 is selected. Signed-off-by: Daniel Palmer Suggested-by: Stephen Boyd Link: https://lore.kernel.org/r/20210215115710.3762276-1-daniel@0x0f.com [sboyd@kernel.org: Drop regmap select too] Signed-off-by: Stephen Boyd

clk: mstar: MStar/SigmaStar MPLL driver

2021-02-14T20:38:00+00:00

This adds a basic driver for the MPLL block found in MStar/SigmaStar ARMv7 SoCs. Currently this driver is only good for calculating the rates of it's outputs and the actual configuration must be done before the kernel boots. Usually this is done even before u-boot starts. This driver targets the MPLL block found in the MSC313/MSC313E but there is no documentation this chip so the register descriptions for the another MStar chip the MST786 were used as they seem to match. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.com Signed-off-by: Stephen Boyd