kernel/linux.git/drivers/clk/mmp/Makefile, branch linux-7.0.y

clk: mmp: pxa1908: Instantiate power driver through auxiliary bus

2025-09-21T17:48:44+00:00

The power domain driver shares the APMU clock controller's registers. Instantiate the power domain driver through the APMU clock driver using the auxiliary bus. Also create a separate Kconfig entry for the PXA1908 clock driver to allow (de)selecting the driver at will and selecting CONFIG_AUXILIARY_BUS. Signed-off-by: Duje Mihanović Signed-off-by: Stephen Boyd

clk: mmp: Add Marvell PXA1908 MPMU driver

2024-11-14T22:33:02+00:00

Add driver for the MPMU controller block on Marvell's PXA1908 SoC. The driver is incomplete, currently only supporting the fixed PLL1; dynamic PLLs 2-4 and CPU/DDR/AXI clock support is missing. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-8-e050609b8d6c@skole.hr Signed-off-by: Stephen Boyd

clk: mmp: Add Marvell PXA1908 APMU driver

2024-11-14T22:33:01+00:00

Add driver for the APMU controller block found on Marvell's PXA1908 SoC. This driver is incomplete, lacking support for (at least) GPU, VPU, DSI and CCIC (camera related) clocks. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-7-e050609b8d6c@skole.hr Signed-off-by: Stephen Boyd

clk: mmp: Add Marvell PXA1908 APBCP driver

2024-11-14T22:32:59+00:00

Add driver for the APBCP controller block found on Marvell's PXA1908 SoC. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-6-e050609b8d6c@skole.hr Signed-off-by: Stephen Boyd

clk: mmp: Add Marvell PXA1908 APBC driver

2024-11-14T22:32:58+00:00

Add driver for the APBC controller block found on Marvell's PXA1908 SoC. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-5-e050609b8d6c@skole.hr Signed-off-by: Stephen Boyd

clk: mmp: Remove old non-OF clock drivers

2023-08-22T21:13:11+00:00

There are no MMP2, PXA168 or PXA910 boards still using board files which would use these drivers, so remove them. Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20230804-drop-old-mmp-clk-v1-1-0c07db6cee90@skole.hr Signed-off-by: Stephen Boyd

clk: mmp2: Add audio clock controller driver

2020-05-28T00:55:12+00:00

This is a driver for a block that generates master and bit clocks for the I2S interface. It's separate from the PMUs that generate clocks for the peripherals. Signed-off-by: Lubomir Rintel Link: https://lkml.kernel.org/r/20200519224151.2074597-14-lkundrak@v3.sk Signed-off-by: Stephen Boyd

clk: mmp2: Add support for power islands

2020-05-28T00:55:12+00:00

Apart from the clocks and resets, the PMU hardware also controls power to peripherals that are on separate power islands. On MMP2, that's the GC860 GPU and the SSPA audio interface, while on MMP3 also the camera interface is on a separate island, along with the pair of GC2000 and GC300 GPUs and the SSPA. Signed-off-by: Lubomir Rintel Link: https://lkml.kernel.org/r/20200519224151.2074597-12-lkundrak@v3.sk Signed-off-by: Stephen Boyd

clk: mmp2: Add support for PLL clock sources

2020-03-21T01:19:31+00:00

The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable. Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. There is no documentation for either SoC, but the "systemsetting" drivers from Marvell GPL code dump provide some clue as far as MPMU registers on MMP2 [1] and MMP3 [2] go. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c A separate commit will adjust the clk-of-mmp2 driver. Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC XO-1.75 laptop. Signed-off-by: Lubomir Rintel Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk Signed-off-by: Stephen Boyd

ARM: mmp: add support for MMP3 SoC

2019-10-17T14:36:11+00:00

Similar to MMP2, which this patch is based on. Known differencies from MMP2 are: * Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes Hard to tell what else is different, because documentation is not available. Signed-off-by: Lubomir Rintel