kernel/linux.git/drivers/clk/microchip, branch v6.18.21

clk: microchip: core: correct return value on *_get_parent()

2026-03-04T12:20:31+00:00

[ Upstream commit 5df96d141cccb37f0c3112a22fc1112ea48e9246 ] roclk_get_parent() and sclk_get_parent() has the possibility of returning -EINVAL, however the framework expects this call to always succeed since the return value is unsigned. If there is no parent map defined, then the current value programmed in the hardware is used. Let's use that same value in the case where -EINVAL is currently returned. This index is only used by clk_core_get_parent_by_index(), and it validates that it doesn't overflow the number of available parents. Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202512050233.R9hAWsJN-lkp@intel.com/ Signed-off-by: Brian Masney Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20251205-clk-microchip-fixes-v3-2-a02190705e47@redhat.com Signed-off-by: Claudiu Beznea Signed-off-by: Sasha Levin

clk: microchip: core: remove duplicate determine_rate on pic32_sclk_ops

2026-02-26T22:59:30+00:00

[ Upstream commit d93faac66dc04650d924f8f9584216d14f48fb14 ] pic32_sclk_ops previously had a sclk_round_rate() member, and this was recently converted over to sclk_determine_rate() with the help of a Coccinelle semantic patch. pic32_sclk_ops now has two conflicting determine_rate ops members. Prior to the conversion, pic32_sclk_ops already had a determine_rate member that points to __clk_mux_determine_rate(). When both the round_rate() and determine_rate() ops are defined, the clk core only uses the determine_rate() op. Let's go ahead and drop the recently converted sclk_determine_rate() to match the previous functionality prior to the conversion. Fixes: e9f039c08cdc ("clk: microchip: core: convert from round_rate() to determine_rate()") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202511222115.uvHrP95A-lkp@intel.com/ Signed-off-by: Brian Masney Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20251205-clk-microchip-fixes-v3-1-a02190705e47@redhat.com Signed-off-by: Claudiu Beznea Signed-off-by: Sasha Levin

clk: microchip: core: remove duplicate roclk_determine_rate()

2025-10-01T04:54:29+00:00

Fix compiler error caused by the round_rate() to determine_rate() migration. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202509280327.jsapR0Ww-lkp@intel.com/ Signed-off-by: Brian Masney Fixes: e9f039c08cdc ("clk: microchip: core: convert from round_rate() to determine_rate()") Signed-off-by: Stephen Boyd

clk: microchip: core: convert from round_rate() to determine_rate()

2025-09-08T13:41:30+00:00

The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney

clk: Fix typos

2025-07-27T06:49:18+00:00

Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and uses updated). Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org Signed-off-by: Stephen Boyd

module: Convert symbol namespace to string literal

2024-12-02T19:34:44+00:00

Clean up the existing export namespace code along the same lines of commit 33def8498fdd ("treewide: Convert macro and uses of __section(foo) to __section("foo")") and for the same reason, it is not desired for the namespace argument to be a macro expansion itself. Scripted using git grep -l -e MODULE_IMPORT_NS -e EXPORT_SYMBOL_NS | while read file; do awk -i inplace ' /^#define EXPORT_SYMBOL_NS/ { gsub(/__stringify$ns$/, "ns"); print; next; } /^#define MODULE_IMPORT_NS/ { gsub(/__stringify$ns$/, "ns"); print; next; } /MODULE_IMPORT_NS/ { $0 = gensub(/MODULE_IMPORT_NS$([^)]*)$/, "MODULE_IMPORT_NS(\"\\1\")", "g"); } /EXPORT_SYMBOL_NS/ { if ($0 ~ /(EXPORT_SYMBOL_NS[^(]*)$([^,]+),/) { if ($0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)$/ && $0 !~ /(EXPORT_SYMBOL_NS[^(]*)/ && $0 !~ /^my/) { getline line; gsub(/[[:space:]]*\\$/, ""); gsub(/[[:space:]]/, "", line); $0 = $0 " " line; } $0 = gensub(/(EXPORT_SYMBOL_NS[^(]*)$([^,]+), ([^)]+)$/, "\\1(\\2, \"\\3\")", "g"); } } { print }' $file; done Requested-by: Masahiro Yamada Signed-off-by: Peter Zijlstra (Intel) Link: https://mail.google.com/mail/u/2/#inbox/FMfcgzQXKWgMmjdFwwdsfgxzKpVHWPlc Acked-by: Greg KH Signed-off-by: Linus Torvalds

clock, reset: microchip: move all mpfs reset code to the reset subsystem

2024-05-07T21:57:46+00:00

Stephen and Philipp, while reviewing patches, said that all of the aux device creation and the register read/write code could be moved to the reset subsystem, leaving the clock driver with no implementations of reset_* functions at all. Move them. Suggested-by: Philipp Zabel Suggested-by: Stephen Boyd Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20240424-strangle-sharpener-34755c5e6e3e@spud Signed-off-by: Stephen Boyd

clk: microchip: mpfs: convert MSSPLL outputs to clk_divider

2024-02-06T14:07:18+00:00

After splitting the MSSPLL in two, the PLL outputs have become open-coded versions of clk_divider. Drop the custom clk ops structs, and instead use the generic clk_divider_ops. Signed-off-by: Conor Dooley

clk: microchip: mpfs: add missing MSSPLL outputs

2024-02-06T14:07:18+00:00

The MSSPLL has 4 outputs, of which only the cpu/axi/ahb clock parent is currently implemented. Add the CAN clock too, as that'll be needed by the driver for the CAN controller and uses output 3. While we are here, the other two missing clocks, used by the eMMC/SD controller and by the "user crypto". Signed-off-by: Conor Dooley

clk: microchip: mpfs: setup for using other mss pll outputs

2024-02-06T14:07:18+00:00

Now that the MSSPLL is split, and the "postdiv" divider of the cpu/AHB/AXI bus clock is represented by its own "hw" struct, make the shifts, register offset and width a parameter of the initialisation macro, rather than using defines that only work for one of the four outputs. Configuring this at initialisaion paves the way for using the other three output clocks, where the register offset, and the bit shift within that register, will differ. Signed-off-by: Conor Dooley