kernel/linux.git/drivers/clk/meson, branch v6.3.2

clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-5-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

clk: meson: sclk-div: switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch sclk-div over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-4-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

clk: meson: dualdiv: switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-dualdiv over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-3-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

clk: meson: mpll: Switch from .round_rate to .determine_rate

2023-01-13T14:14:12+00:00

clk_ops.round_rate will be removed at some point. It's replacement is .determine_rate. Switch clk-mpll over to use .determine_rate. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20221225212632.2760126-2-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next

2022-12-12T19:12:52+00:00

* clk-bindings: dt-bindings: clock: ti,cdce925: Convert to DT schema * clk-renesas: (26 commits) clk: renesas: r8a779f0: Fix Ethernet Switch clocks clk: renesas: r8a779g0: Add Z0 clock support clk: renesas: r8a779g0: Add CMT clocks clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks clk: renesas: r8a779f0: Fix SCIF parent clocks clk: renesas: r8a779f0: Fix HSCIF parent clocks clk: renesas: r9a06g032: Repair grave increment error clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc clk: renesas: r8a779a0: Fix SD0H clock name clk: renesas: r8a779g0: Add RPC-IF clock clk: renesas: r8a779g0: Add SDHI clocks clk: renesas: r8a779f0: Add SASYNCPER internal clock clk: renesas: r8a779f0: Fix SD0H clock name clk: renesas: r9a07g043: Drop WDT2 clock and reset entry clk: renesas: r9a07g044: Drop WDT2 clock and reset entry clk: renesas: r8a779g0: Add TPU clock clk: renesas: r8a779g0: Add PWM clock clk: renesas: r8a779g0: Add SCIF clocks clk: renesas: r9a07g044: Add MTU3a clock and reset entry ... * clk-amlogic: clk: meson: pll: add pcie lock retry workaround clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock() * clk-allwinner: clk: sunxi-ng: f1c100s: Add IR mod clock clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.h * clk-ti: clk: ti: fix typo in ti_clk_retry_init() code comment clk: ti: dra7-atl: don't allocate `parent_names' variable clk: ti: change ti_clk_register[_omap_hw]() API

clk: Remove a useless include

2022-11-23T01:52:07+00:00

is not needed for these drivers. Remove the corresponding #include. Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr Acked-by: Heiko Stuebner Acked-by: Jerome Brunet Reviewed-by: Luca Ceresoli Signed-off-by: Stephen Boyd

clk: meson: pll: add pcie lock retry workaround

2022-11-08T16:05:02+00:00

The PCIe PLL locking may be unreliable under some circumstance, such as high or low temperature. If the PLL fails to lock, reset it a try again. This helps on the S905X4 Signed-off-by: Heiner Kallweit [commit message amend] Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/cc80cda0-4dda-2e3e-3fc8-afa97717479b@gmail.com

clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()

2022-11-08T16:05:02+00:00

Currently we loop over meson_parm_read() up to 24mln times. This results in a unpredictable timeout period. In my case it's over 5s on a S905X4-based system. Make the timeout period predictable and set it to 100ms. Signed-off-by: Heiner Kallweit Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/a801afc0-a8f2-a0a4-0f2b-a7201351d563@gmail.com

clk: meson: Hold reference returned by of_get_parent()

2022-08-19T21:29:00+00:00

We should hold the reference returned by of_get_parent() and use it to call of_node_put() for refcount balance. Fixes: 88e2da81241e ("clk: meson: aoclk: refactor common code into dedicated file") Fixes: 6682bd4d443f ("clk: meson: factorise meson64 peripheral clock controller drivers") Fixes: bb6eddd1d28c ("clk: meson: meson8b: use the HHI syscon if available") Signed-off-by: Liang He Link: https://lore.kernel.org/r/20220628141038.168383-1-windhl@126.com Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Stephen Boyd

clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()

2022-06-16T02:22:29+00:00

The clk API just got a function with a slightly different name and the same functionality. Remove the duplication. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20220520075737.758761-5-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd