kernel/linux.git/drivers/clk/meson, branch v5.18.2

clk: cleanup comments

2022-03-12T02:22:15+00:00

For spdx Space instead of tab before spdx tag Removed repeated works the, to, two Replacements much much to a much 'to to' to 'to do' aready to already Comunications to Communications freqency to frequency Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20220222195153.3817625-1-trix@redhat.com Signed-off-by: Stephen Boyd

clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB

2021-11-30T09:28:52+00:00

There are reports that 48kHz audio does not work on the WeTek Play 2 (which uses a GXBB SoC), while 44.1kHz audio works fine on the same board. There are also reports of 48kHz audio working fine on GXL and GXM SoCs, which are using an (almost) identical AIU (audio controller). Experimenting has shown that MPLL0 is causing this problem. In the .dts we have by default: assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; The MPLL0 rate is divisible by 48kHz without remainder and the MPLL1 rate is divisible by 44.1kHz without remainder. Swapping these two clock rates "fixes" 48kHz audio but breaks 44.1kHz audio. Everything looks normal when looking at the info provided by the common clock framework while playing 48kHz audio (via I2S with mclk-fs = 256): mpll_prediv 1 1 0 2000000000 mpll0_div 1 1 0 294909641 mpll0 1 1 0 294909641 cts_amclk_sel 1 1 0 294909641 cts_amclk_div 1 1 0 12287902 cts_amclk 1 1 0 12287902 meson-clk-msr however shows that the actual MPLL0 clock is off by more than 38MHz: mp0_out 333322917 +/-10416Hz The rate seen by meson-clk-msr is very close to what we would get when SDM (the fractional part) was ignored: (2000000000Hz * 16384) / ((16384 * 6) = 333.33MHz If SDM was considered the we should get close to: (2000000000Hz * 16384) / ((16384 * 6) + 12808) = 294.9MHz Further experimenting shows that HHI_MPLL_CNTL7[15] does not have any effect on the rate of MPLL0 as seen my meson-clk-msr (regardless of whether that bit is zero or one the rate is always the same according to meson-clk-msr). Using HHI_MPLL_CNTL[25] on the other hand as SDM_EN results in SDM being considered for the rate output by the hardware. The rate - as seen by meson-clk-msr - matches with what we expect when SDM_EN is enabled (fractional part is being considered, resulting in a 294.9MHz output) or disable (fractional part being ignored, resulting in a 333.33MHz output). Reported-by: Christian Hewitt Tested-by: Christian Hewitt Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20211031135006.1508796-1-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Make the video clock trees mutable

2021-09-23T09:46:38+00:00

Switch from the "_ro" clock op variants to the mutable ones for all video clocks. This will allow the VPU driver to change the clocks as needed for the different video output modes. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-6-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Initialize the HDMI PLL registers

2021-09-23T09:46:37+00:00

Add the reg_sequence to initialize the HDMI PLL with the settings for a video mode that doesn't require PLL internal clock doubling. These settings are taken from the 3.10 vendor kernel's driver for the 2970MHz PLL setting used for the 1080P video mode. This puts the PLL into a defined state and the Linux kernel can take over. While not all bits for this PLL are implemented using these "defaults" and then applying M, N and FRAC seems to work fine. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-5-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Add the HDMI PLL M/N parameters

2021-09-23T09:46:37+00:00

The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter combinations. The PLL won't lock for values smaller than 50 if the internal doubling (which is yet unknown how to use it) is disabled. However, when this doubling is enabled then the values smaller than 50 will lock just fine. The only restriction for values greater than 50 is that the resulting frequency must not exceed the 3.0GHz limit. These values are taken from the endlessm 3.10 kernel which includes additional M/N combinations for some VESA and 75Hz display modes. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-4-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Add the vid_pll_lvds_en gate clock

2021-09-23T09:46:37+00:00

HHI_VID_DIVIDER_CNTL[11] must be enabled for the video clock tree to work. This bit is described as "LVDS_CLK_EN". It is not 100% clear where this bit has to be placed in the hierarchy. But since the "LVDS_OUT" of the HDMI PLL uses it's own set of registers it's more likely that this "LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out" clock to the "vid_pll_in_sel" tree. Add a gate definition for this bit (which will not be exported) so that the kernel can manage all required bits to enable and disable the video clocks. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-3-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel

2021-09-23T09:46:37+00:00

Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only parent which is actually used is vid_pll_final_div. This should be set using assigned-clock-parents in the .dts rather than removing some "unwanted" clock parents from the clock driver. Suggested-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-2-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Export the video clocks

2021-09-23T09:46:37+00:00

Setting the video clocks requires fine-tuned adjustments of various video clocks. Export the required ones to allow changing the video clock for the CVBS and HDMI outputs at runtime. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210713232510.3057750-7-martin.blumenstingl@googlemail.com

clk: meson: regmap: switch to determine_rate for the dividers

2021-06-30T18:37:02+00:00

This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Reviewed-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210627223959.188139-4-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd

clk: meson: g12a: Add missing NNA source clocks for g12b

2021-06-09T19:39:50+00:00

This adds the Neural Network Accelerator source clocks for g12b. Initial support for sm1 already exist in commit 2f1efa5340ef ("clk: meson: g12a: Add support for NNA CLK source clocks") The sm1 and g12b share the same NNA source clocks. This patch add missing NNA clocks for A311D (g12b). Signed-off-by: Nick Xie Acked-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20210604032957.224496-1-xieqinick@gmail.com