kernel/linux.git/drivers/clk/meson/Makefile, branch linux-7.0.y

clk: meson: t7: add t7 clock peripherals controller driver

2025-12-15T09:42:29+00:00

Add Peripheral clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu Link: https://lore.kernel.org/r/20251212022619.3072132-6-jian.hu@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: t7: add support for the T7 SoC PLL clock

2025-12-15T09:42:29+00:00

Add PLL clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu Link: https://lore.kernel.org/r/20251212022619.3072132-5-jian.hu@amlogic.com Signed-off-by: Jerome Brunet

clk: amlogic: drop meson-clkcee

2025-09-04T16:27:12+00:00

What is being done by the Amlogic clock controller registration helper for EE controllers could benefit other controllers. As such, having a specific module for this makes little sense. Move the helper function to clkc-utils and rename it to describe what it does, registering syscon based controller, instead of what it serves. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-1-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet

clk: meson: c3: add c3 clock peripherals controller driver

2024-06-04T08:38:32+00:00

Add the C3 peripherals clock controller driver in the C3 SoC family. [jbrunet: fix Kconfig select order and probe function name] Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240522082727.3029656-6-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: c3: add support for the C3 SoC PLL clock

2024-06-04T08:38:16+00:00

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family. [jbrunet: fixed probe function name] Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: add vclk driver

2024-04-10T07:46:21+00:00

The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet

clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

2023-09-27T09:01:03+00:00

Add the peripherals clock controller driver in the S4 SoC family. [jbrunet: remove extra new line at end of s4-peripherals.h] Signed-off-by: Yu Tu Link: https://lore.kernel.org/r/20230904075504.23263-5-yu.tu@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

2023-09-27T08:54:24+00:00

Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: introduce meson-clkc-utils

2023-08-08T14:06:16+00:00

Let's introduce a new module called meson-clkc-utils that will contain shared utility functions for all Amlogic clock controller drivers. The first utility function is a replacement of of_clk_hw_onecell_get in order to get rid of the NR_CLKS define in all Amlogic clock drivers. The goal is to move all duplicate probe and init code in this module. [jbrunet: Fixed MODULE_LICENCE checkpatch warning] Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet

clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

2023-05-30T15:53:09+00:00

Introduce Peripherals clock controller for Amlogic A1 SoC family. A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU, and Audio. This patchset adds support for Amlogic A1 Peripherals clock driver and allows to generate clocks for all A1 SoC peripheral IPs. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230523135351.19133-7-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet