kernel/linux.git/drivers/clk/mediatek, branch v5.15.209

clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data

2023-11-20T10:08:18+00:00

[ Upstream commit 0d6e24b422a2166a9297a8286ff2e6ab9a5e8cd3 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230901024658.23405-1-jiasheng@iscas.ac.cn Reviewed-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: clk-mt7629: Add check for mtk_alloc_clk_data

2023-11-20T10:08:18+00:00

[ Upstream commit 2befa515c1bb6cdd33c262b909d93d1973a219aa ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230912093407.21505-5-jiasheng@iscas.ac.cn Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data

2023-11-20T10:08:18+00:00

[ Upstream commit 0884393c63cc9a1772f7121a6645ba7bd76feeb9 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230912093407.21505-4-jiasheng@iscas.ac.cn Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data

2023-11-20T10:08:18+00:00

[ Upstream commit 606f6366a35a3329545e38129804d65ef26ed7d2 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230912093407.21505-3-jiasheng@iscas.ac.cn Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: clk-mt6779: Add check for mtk_alloc_clk_data

2023-11-20T10:08:18+00:00

[ Upstream commit 1f57f78fbacf630430bf954e5a84caafdfea30c0 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230912093407.21505-2-jiasheng@iscas.ac.cn Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_data

2023-11-20T10:08:18+00:00

[ Upstream commit b82681042724924ae3ba0f2f2eeec217fa31e830 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230912093407.21505-1-jiasheng@iscas.ac.cn Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent

2022-10-26T10:35:18+00:00

[ Upstream commit 9f94f545f258b15bfa6357eb62e1e307b712851e ] The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai Signed-off-by: Sasha Levin

clk: mediatek: reset: Fix written reset bit offset

2022-08-17T12:23:43+00:00

[ Upstream commit edabcf71d100fd433a0fc2d0c97057c446c33b2a ] Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220523093346.28493-3-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167

2021-07-27T18:46:27+00:00

I found that COMMON_CLK_MT8167* do not depend on COMMON_CLK_MT8167, so it is possible to config: CONFIG_COMMON_CLK_MT8167=n CONFIG_COMMON_CLK_MT8167_*=y Although it does not cause build breaks with such configuration, I think it is clearer to make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167. Signed-off-by: Miles Chen Link: https://lore.kernel.org/r/20210716051732.3422-1-miles.chen@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8192 vencsys clock support

2021-07-27T17:53:10+00:00

Add MT8192 vencsys clock provider Signed-off-by: Weiyi Lu Signed-off-by: Chun-Jie Chen Link: https://lore.kernel.org/r/20210726105719.15793-22-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang Signed-off-by: Stephen Boyd