kernel/linux.git/drivers/clk/mediatek, branch linux-4.20.y

clk: mediatek: remove unused array audio_parents

2018-08-31T01:29:36+00:00

Array audio_parents is declared but never used, hence it is redundant and can be removed. Cleans up clang warning: warning: 'audio_parents' defined but not used [-Wunused-const-variable=] Signed-off-by: Colin Ian King Signed-off-by: Stephen Boyd

Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next

2018-06-04T19:27:40+00:00

* clk-hisi-usb: clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC * clk-silent-bulk: clk: bulk: silently error out on EPROBE_DEFER * clk-mtk-hdmi: clk: mediatek: correct the clocks for MT2701 HDMI PHY module * clk-mtk-mali: clk: mediatek: add g3dsys support for MT2701 and MT7623 dt-bindings: reset: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add g3dsys bindings * clk-imx6ul-ccosr: clk: imx: Add new clo01 and clo2 controlled by CCOSR

clk: mediatek: add g3dsys support for MT2701 and MT7623

2018-05-15T22:21:36+00:00

Add clock driver support for g3dsys on MT2701 and MT7623, which is providing essential clock gate and reset controller to Mali-450. Signed-off-by: Sean Wang Signed-off-by: Stephen Boyd

clk: mediatek: correct the clocks for MT2701 HDMI PHY module

2018-05-15T22:17:49+00:00

The hdmitx_dig_cts clock signal is not a child of clk26m, and the actual output of the PLL block is derived from the tvdpll via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Chunhui Dai Signed-off-by: Ryder Lee Signed-off-by: Stephen Boyd

Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next

2018-04-06T20:21:57+00:00

* clk-mediatek: clk: mediatek: add audsys support for MT2701 clk: mediatek: add devm_of_platform_populate() for MT7622 audsys dt-bindings: clock: mediatek: add audsys support for MT2701 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device clk: mediatek: update missing clock data for MT7622 audsys clk: mediatek: fix PWM clock source by adding a fixed-factor clock dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 * clk-hisi: clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc() clk: hisilicon: mark wdt_mux_p[] as const clk: hisilicon: Mark phase_ops static clk: hi3798cv200: add emmc sample and drive clock clk: hisilicon: add hisi phase clock support clk: hi3798cv200: add COMBPHY0 clock support clk: hi3798cv200: fix define indentation clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK clk: hi3798cv200: correct IR clock parent clk: hi3798cv200: fix unregister call sequence in error path * clk-allwinner: clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU clk: sunxi-ng: add support for the Allwinner H6 CCU dt-bindings: add device tree binding for Allwinner H6 main CCU clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate clk: sunxi-ng: h3: h5: Add minimal rate for video PLL clk: sunxi-ng: Add check for minimal rate to NM PLLs clk: sunxi-ng: Use u64 for calculation of nkmp rate clk: sunxi-ng: Mask nkmp factors when setting register clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name * clk-ux500: clk: ux500: Drop AB8540/9540 support * clk-renesas: (27 commits) clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: fix false-positive Wmaybe-uninitialized warning clk: renesas: r8a77965: Replace DU2 clock clk: renesas: cpg-mssr: Add support for R-Car M3-N clk: renesas: cpg-mssr: add R8A77980 support dt-bindings: clock: add R8A77980 CPG core clock definitions clk: renesas: r8a7792: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7743: Add rwdt clock ...

clk: mediatek: add audsys support for MT2701

2018-03-20T07:24:42+00:00

Add clock driver support for MT2701 audsys. Signed-off-by: Ryder Lee Signed-off-by: Stephen Boyd

clk: mediatek: add devm_of_platform_populate() for MT7622 audsys

2018-03-20T07:24:33+00:00

Add devm_of_platform_populate() to populate devices which are children of the root node. Signed-off-by: Ryder Lee Signed-off-by: Stephen Boyd

clk: mediatek: update clock driver of MT2712

2018-03-19T21:37:40+00:00

According to ECO design change, 1. add new clock mux data and change some 2. add new clock gate data and clock factor data 3. change status register offset of infra subsystem Signed-off-by: Weiyi Lu Signed-off-by: Stephen Boyd

clk: mediatek: update missing clock data for MT7622 audsys

2018-03-19T20:40:57+00:00

Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger Signed-off-by: Stephen Boyd

clk: mediatek: fix PWM clock source by adding a fixed-factor clock

2018-03-19T20:25:30+00:00

The clock for which all PWM devices on MT7623 or MT2701 actually depending on has to be divided by four from its parent clock axi_sel in the clock path prior to PWM devices. Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of clock axi_sel allows that PWM devices can have the correct resolution calculation. Cc: stable@vger.kernel.org Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Sean Wang Signed-off-by: Stephen Boyd