<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/clk/keystone, branch v6.1.168</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-11-20T10:51:56+00:00</updated>
<entry>
<title>clk: keystone: pll: fix a couple NULL vs IS_ERR() checks</title>
<updated>2023-11-20T10:51:56+00:00</updated>
<author>
<name>Dan Carpenter</name>
<email>dan.carpenter@linaro.org</email>
</author>
<published>2023-10-05T14:01:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cb6c38995f9c680847f3e2395f87cc7cfd6cebfa'/>
<id>urn:sha1:cb6c38995f9c680847f3e2395f87cc7cfd6cebfa</id>
<content type='text'>
[ Upstream commit a5d14f8b551eb1551c10053653ee8e27f19672fa ]

The clk_register_divider() and clk_register_mux() functions returns
error pointers on error but this code checks for NULL.  Fix that.

Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver")
Signed-off-by: Dan Carpenter &lt;dan.carpenter@linaro.org&gt;
Link: https://lore.kernel.org/r/d9da4c97-0da9-499f-9a21-1f8e3f148dc1@moroto.mountain
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()</title>
<updated>2023-09-13T07:42:45+00:00</updated>
<author>
<name>Minjie Du</name>
<email>duminjie@vivo.com</email>
</author>
<published>2023-07-12T10:22:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4a43285900cd4e686f7e9113876a3697b206f180'/>
<id>urn:sha1:4a43285900cd4e686f7e9113876a3697b206f180</id>
<content type='text'>
[ Upstream commit a995c50db887ef97f3160775aef7d772635a6f6e ]

The function clk_register_pll() may return NULL or an ERR_PTR. Don't
treat an ERR_PTR as valid.

Signed-off-by: Minjie Du &lt;duminjie@vivo.com&gt;
Link: https://lore.kernel.org/r/20230712102246.10348-1-duminjie@vivo.com
Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver")
[sboyd@kernel.org: Reword commit text]
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: keystone: sci-clk: check return value of kasprintf()</title>
<updated>2023-07-19T14:21:33+00:00</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2023-05-30T09:39:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=67684f0688deda40bff928bf45891185b783dc33'/>
<id>urn:sha1:67684f0688deda40bff928bf45891185b783dc33</id>
<content type='text'>
[ Upstream commit b73ed981da6d25c921aaefa7ca3df85bbd85b7fc ]

kasprintf() returns a pointer to dynamically allocated memory.
Pointer could be NULL in case allocation fails. Check pointer validity.
Identified with coccinelle (kmerr.cocci script).

Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support")
Depends-on: 96488c09b0f4 ("clk: keystone: sci-clk: cut down the clock name length")
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Link: https://lore.kernel.org/r/20230530093913.1656095-7-claudiu.beznea@microchip.com
Reviewed-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE</title>
<updated>2022-06-10T12:51:36+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2022-06-07T14:11:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5a729246e57eac410e4a13f5aba66ae2dc552632'/>
<id>urn:sha1:5a729246e57eac410e4a13f5aba66ae2dc552632</id>
<content type='text'>
Based on the normalized pattern:

    this program is free software you can redistribute it and/or modify it
    under the terms of the gnu general public license version 2 as
    published by the free software foundation  this program is distributed
    as is without any warranty of any kind whether express or implied
    without even the implied warranty of merchantability or fitness for a
    particular purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

has been chosen to replace the boilerplate/reference.

Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>clk: keystone: syscon-clk: Add support for AM62 epwm-tbclk</title>
<updated>2022-04-23T02:04:47+00:00</updated>
<author>
<name>Georgi Vlaev</name>
<email>g-vlaev@ti.com</email>
</author>
<published>2022-04-15T19:03:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bae71de51b8901372d7ed5c6b89d32282db7e9ed'/>
<id>urn:sha1:bae71de51b8901372d7ed5c6b89d32282db7e9ed</id>
<content type='text'>
AM62 has 3 instances of EPWM modules. Each EPWM module has
an EPWM TBCLKEN module input used to individually enable or
disable its EPWM time-base clock. The EPWM time-base clock
enable input comes from the CTRLMMR_EPWM_TB_CLKEN register
bits 0 to 2 in CTRL_MMR0 module (6.1.1.4.1.48 [1]). This
is virtually the same setup as in AM64 but with 3 instead
of 9 clock providers on AM62.

Update the driver with the 3 instances of clocks associated
to a new compatible: "ti,am62-epwm-tbclk".

[1] https://www.ti.com/lit/pdf/spruiv7

Signed-off-by: Georgi Vlaev &lt;g-vlaev@ti.com&gt;
Tested-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Link: https://lore.kernel.org/r/20220415190343.6284-3-g-vlaev@ti.com
Reviewed-by: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk</title>
<updated>2021-06-22T21:18:26+00:00</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2021-05-28T04:57:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=87e2a58ca6c7095e5dc43e25212183afbfe0ad64'/>
<id>urn:sha1:87e2a58ca6c7095e5dc43e25212183afbfe0ad64</id>
<content type='text'>
AM64 has 9 instances of EPWM modules. And each instance has a clk to
Timer-Base sub-module that can be controlled by Control module. Update
the driver with all the 9 instance of clocks associated to
ti,am64-epwm-tbclk.

Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Link: https://lore.kernel.org/r/20210528045743.16537-3-lokeshvutla@ti.com
Reviewed-by: Tero Kristo &lt;kristo@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>treewide: Change list_sort to use const pointers</title>
<updated>2021-04-08T23:04:22+00:00</updated>
<author>
<name>Sami Tolvanen</name>
<email>samitolvanen@google.com</email>
</author>
<published>2021-04-08T18:28:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4f0f586bf0c898233d8f316f471a21db2abd522d'/>
<id>urn:sha1:4f0f586bf0c898233d8f316f471a21db2abd522d</id>
<content type='text'>
list_sort() internally casts the comparison function passed to it
to a different type with constant struct list_head pointers, and
uses this pointer to call the functions, which trips indirect call
Control-Flow Integrity (CFI) checking.

Instead of removing the consts, this change defines the
list_cmp_func_t type and changes the comparison function types of
all list_sort() callers to use const pointers, thus avoiding type
mismatches.

Suggested-by: Nick Desaulniers &lt;ndesaulniers@google.com&gt;
Signed-off-by: Sami Tolvanen &lt;samitolvanen@google.com&gt;
Reviewed-by: Nick Desaulniers &lt;ndesaulniers@google.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Kees Cook &lt;keescook@chromium.org&gt;
Tested-by: Nick Desaulniers &lt;ndesaulniers@google.com&gt;
Tested-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
Signed-off-by: Kees Cook &lt;keescook@chromium.org&gt;
Link: https://lore.kernel.org/r/20210408182843.1754385-10-samitolvanen@google.com
</content>
</entry>
<entry>
<title>clk: keystone: sci-clk: add 10% slack to set_rate</title>
<updated>2020-09-22T19:58:52+00:00</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-09-07T08:57:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4630ef134e41389a7170b05790c0ddcd88977b01'/>
<id>urn:sha1:4630ef134e41389a7170b05790c0ddcd88977b01</id>
<content type='text'>
Currently, we request exact clock rates from the firmware to be set with
set_rate. Due to some rounding errors and internal functionality of the
firmware itself, this can fail. Thus, add some slack to the set_rate
functionality so that we are always guaranteed to pass. The firmware
always attempts to use frequency as close to the target freq as
possible despite the slack given here.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Link: https://lore.kernel.org/r/20200907085740.1083-4-t-kristo@ti.com
Acked-by: Santosh Shilimkar &lt;ssantosh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: keystone: sci-clk: cache results of last query rate operation</title>
<updated>2020-09-22T19:58:43+00:00</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-09-07T08:57:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d3f3f499cb335eba84788a9456f7d6f92a069bbe'/>
<id>urn:sha1:d3f3f499cb335eba84788a9456f7d6f92a069bbe</id>
<content type='text'>
Cache results of the latest query rate operation. This optimizes the
firmware interface a bit, avoiding unnecessary calls to firmware if we
know the result already; the firmware interface is pretty expensive
to use for query rate functionality.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Link: https://lore.kernel.org/r/20200907085740.1083-3-t-kristo@ti.com
Acked-by: Santosh Shilimkar &lt;ssantosh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: keystone: sci-clk: fix parsing assigned-clock data during probe</title>
<updated>2020-09-22T19:58:34+00:00</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2020-09-07T08:57:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2f05cced7307489faab873367fb20cd212e1d890'/>
<id>urn:sha1:2f05cced7307489faab873367fb20cd212e1d890</id>
<content type='text'>
The DT clock probe loop incorrectly terminates after processing "clocks"
only, fix this by re-starting the loop when all entries for current
DT property have been parsed.

Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware")
Reported-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Link: https://lore.kernel.org/r/20200907085740.1083-2-t-kristo@ti.com
Acked-by: Santosh Shilimkar &lt;ssantosh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
</feed>
