kernel/linux.git/drivers/clk/keystone, branch v3.18.62

clk: keystone: add support for post divider register for main pll

2015-08-22T18:05:31+00:00

[ Upstream commit 02fdfd708fd252a778709beb6c65d5e7360341ac ] Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri Signed-off-by: Michael Turquette Signed-off-by: Sasha Levin

clk: keystone: gate: fix clk_init_data initialization

2014-02-10T20:17:43+00:00

The clk_init_data struct is allocated in the stack. All members of this struct should be initialized before using otherwise it will lead to unpredictable situation as it can contain garbage. Ultimately the clk->flag field contains garbage. In my case it leads that flag CLK_IGNORE_UNUSED is set for most of clocks. As result a bunch of unused clocks cannot be disabled. So initialize flags in this structure too. Cc: Mike Turquette Signed-off-by: Ivan Khoronzhuk Signed-off-by: Santosh Shilimkar

clk: keystone: gate: fix error handling on init

2013-12-10T16:08:20+00:00

This patch fixes Keystone gate control clock driver initialization path: 1) clk_register_psc() returns error code and not a pure pointer, hence its return value need to be checked using IS_ERR(clk) macro. 2) Mapped IO memory isn't unmapped in case of errors, hence fix it. Cc: Mike Turquette Signed-off-by: Santosh Shilimkar

clk: keystone: use clkod register bits for postdiv

2013-12-10T16:08:20+00:00

DDR3A/B, ARM and PA PLL controllers have clkod register bits for configuring postdiv values. So use it instead of using fixed post dividers for these pll controllers. Assume that if fixed-postdiv attribute is not present, use clkod register value for pistdiv. Also update the Documentation of bindings to reflect the same. Cc: Mike Turquette Signed-off-by: Santosh Shilimkar

clk: keystone: Build Keystone clock drivers

2013-10-08T01:16:37+00:00

Now build the keystone common clock drivers. The build is made conditional based on COMMON_CLK_KEYSTONE Signed-off-by: Santosh Shilimkar Signed-off-by: Mike Turquette

clk: keystone: Add gate control clock driver

2013-10-08T01:16:30+00:00

Add the driver for the clock gate control which uses PSC (Power Sleep Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and disabling of the clocks for different IPs present in the SoC. Signed-off-by: Santosh Shilimkar Signed-off-by: Mike Turquette

clk: keystone: add Keystone PLL clock driver

2013-10-08T01:16:21+00:00

Add the driver for the PLL IPs found on Keystone 2 devices. The PLL IP typically has a multiplier, a divider and a post-divider. The PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main PLL is controlled by a PLL controller and memory map registers. Signed-off-by: Santosh Shilimkar Signed-off-by: Mike Turquette