kernel/linux.git/drivers/clk/clk_test.c, branch linux-7.1.y

clk: test: remove references to clk_ops.round_rate

2026-02-22T22:38:20+00:00

The round_rate() clk ops is going away, so let's go ahead and remove any references to it in the comments. Signed-off-by: Brian Masney

Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next

2025-07-29T22:18:13+00:00

- Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers * clk-bindings: (30 commits) dt-bindings: clock: convert lpc1850-cgu.txt to yaml format dt-bindings: clock: Convert qca,ath79-pll to DT schema dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema dt-bindings: clock: Convert moxa,moxart-clock to DT schema dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema dt-bindings: clock: Convert maxim,max9485 to DT schema dt-bindings: clock: Convert qcom,krait-cc to DT schema dt-bindings: clock: qcom: Remove double colon from description dt-bindings: clock: convert lpc1850-ccu.txt to yaml format dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema dt-bindings: clock: Convert marvell,berlin2-clk to DT schema dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema dt-bindings: clock: Convert lsi,axm5516-clks to DT schema ... * clk-cleanup: (29 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: bcm: bcm2835: convert from round_rate() to determine_rate() MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry clk: ti: Simplify ti_find_clock_provider() ... * clk-pwm: clk: pwm: Make use of non-sleeping PWMs clk: pwm: Don't reconfigure running PWM at probe time clk: pwm: Convert to use pwm_apply_might_sleep() clk: pwm: Let .get_duty_cycle() return the real duty cycle * clk-hw-device: clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests clk: tests: Make clk_register_clk_parent_data_device_driver() common clk: add a clk_hw helpers to get the clock device or device_node * clk-xilinx: clk: xilinx: vcu: Update vcu init/reset sequence clk: xilinx: vcu: unregister pll_post only if registered correctly * clk-adi: clk: clk-axi-clkgen: fix coding style issues clk: clk-axi-clkgen move to min/max() clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime include: adi-axi-common: add new helper macros include: linux: move adi-axi-common.h out of fpga clk: clk-axi-clkgen: make sure to include mod_devicetable.h clk: clk-axi-clkgen: fix fpfd_max frequency for zynq

clk: Fix typos

2025-07-27T06:49:18+00:00

Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and uses updated). Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org Signed-off-by: Stephen Boyd

clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests

2025-06-20T07:15:39+00:00

Add kunit test suites clk_hw_get_dev() and clk_hw_get_of_node() for clocks registered with clk_hw_register() and of_clk_hw_register() Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-2-7743e509612a@baylibre.com Reviewed-by: Brian Masney [sboyd@kernel.org: Drop genparams, rename tests, drop inits, combine suites, add test for non-DT platform device] Signed-off-by: Stephen Boyd

clk: tests: Make clk_register_clk_parent_data_device_driver() common

2025-06-20T07:15:06+00:00

Rename clk_register_clk_parent_data_device_driver() to kunit_of_platform_driver_dev() and have it return a struct device pointer while accepting a match table. This will be useful to find the device associated with an OF node for more tests than only the clk_parent_data tests. Signed-off-by: Jerome Brunet [sboyd@kernel.org: Split out from next patch, carry SoB and authorship, rename API, return device pointer] Signed-off-by: Stephen Boyd

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2024-11-23T01:02:25+00:00

Pull clk updates from Stephen Boyd: "The core framework gained a clk provider helper, a clk consumer helper, and some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access clk: Fix invalid execution of clk_set_rate clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider clk: lan966x: make it selectable for ARCH_LAN969X clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one ...

clk: test: Fix some memory leaks

2024-10-16T21:39:18+00:00

CONFIG_CLK_KUNIT_TEST=y, CONFIG_DEBUG_KMEMLEAK=y and CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y, the following memory leak occurs. If the KUNIT_ASSERT_*() fails, the latter (exit() or testcases) clk_put() or clk_hw_unregister() will fail to release the clk resource and cause memory leaks, use new clk_hw_register_kunit() and clk_hw_get_clk_kunit() to automatically release them. unreferenced object 0xffffff80c6af5000 (size 512): comm "kunit_try_catch", pid 371, jiffies 4294896001 hex dump (first 32 bytes): 20 4c c0 86 e1 ff ff ff e0 1a c0 86 e1 ff ff ff L.............. c0 75 e3 c6 80 ff ff ff 00 00 00 00 00 00 00 00 .u.............. backtrace (crc 8ca788fa): [<00000000e21852d0>] kmemleak_alloc+0x34/0x40 [<000000009c583f7b>] __kmalloc_cache_noprof+0x26c/0x2f4 [<00000000d1bc850c>] __clk_register+0x80/0x1ecc [<00000000b08c78c5>] clk_hw_register+0xc4/0x110 [<00000000b16d6df8>] clk_multiple_parents_mux_test_init+0x238/0x288 [<0000000014a7e804>] kunit_try_run_case+0x10c/0x3ac [<0000000026b41f03>] kunit_generic_run_threadfn_adapter+0x80/0xec [<0000000066619fb8>] kthread+0x2e8/0x374 [<00000000a1157f53>] ret_from_fork+0x10/0x20 unreferenced object 0xffffff80c6e37880 (size 96): comm "kunit_try_catch", pid 371, jiffies 4294896002 hex dump (first 32 bytes): 00 50 af c6 80 ff ff ff 00 00 00 00 00 00 00 00 .P.............. 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace (crc b4b766dd): [<00000000e21852d0>] kmemleak_alloc+0x34/0x40 [<000000009c583f7b>] __kmalloc_cache_noprof+0x26c/0x2f4 [<0000000086e7dd64>] clk_hw_create_clk.part.0.isra.0+0x58/0x2f4 [<00000000dcf1ac31>] clk_hw_get_clk+0x8c/0x114 [<000000006fab5bfa>] clk_test_multiple_parents_mux_set_range_set_parent_get_rate+0x3c/0xa0 [<00000000c97db55a>] kunit_try_run_case+0x13c/0x3ac [<0000000026b41f03>] kunit_generic_run_threadfn_adapter+0x80/0xec [<0000000066619fb8>] kthread+0x2e8/0x374 [<00000000a1157f53>] ret_from_fork+0x10/0x20 unreferenced object 0xffffff80c2b56900 (size 96): comm "kunit_try_catch", pid 395, jiffies 4294896107 hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 e0 49 c0 86 e1 ff ff ff .........I...... backtrace (crc 2e59b327): [<00000000e21852d0>] kmemleak_alloc+0x34/0x40 [<00000000c6c715a8>] __kmalloc_noprof+0x2bc/0x3c0 [<00000000f04a7951>] __clk_register+0x70c/0x1ecc [<00000000b08c78c5>] clk_hw_register+0xc4/0x110 [<00000000cafa9563>] clk_orphan_transparent_multiple_parent_mux_test_init+0x1a8/0x1dc [<0000000014a7e804>] kunit_try_run_case+0x10c/0x3ac [<0000000026b41f03>] kunit_generic_run_threadfn_adapter+0x80/0xec [<0000000066619fb8>] kthread+0x2e8/0x374 [<00000000a1157f53>] ret_from_fork+0x10/0x20 unreferenced object 0xffffff80c87c9400 (size 512): comm "kunit_try_catch", pid 483, jiffies 4294896907 hex dump (first 32 bytes): a0 44 c0 86 e1 ff ff ff e0 1a c0 86 e1 ff ff ff .D.............. 20 05 a8 c8 80 ff ff ff 00 00 00 00 00 00 00 00 ............... backtrace (crc c25b43fb): [<00000000e21852d0>] kmemleak_alloc+0x34/0x40 [<000000009c583f7b>] __kmalloc_cache_noprof+0x26c/0x2f4 [<00000000d1bc850c>] __clk_register+0x80/0x1ecc [<00000000b08c78c5>] clk_hw_register+0xc4/0x110 [<000000002688be48>] clk_single_parent_mux_test_init+0x1a0/0x1d4 [<0000000014a7e804>] kunit_try_run_case+0x10c/0x3ac [<0000000026b41f03>] kunit_generic_run_threadfn_adapter+0x80/0xec [<0000000066619fb8>] kthread+0x2e8/0x374 [<00000000a1157f53>] ret_from_fork+0x10/0x20 unreferenced object 0xffffff80c6dd2380 (size 96): comm "kunit_try_catch", pid 483, jiffies 4294896908 hex dump (first 32 bytes): 00 94 7c c8 80 ff ff ff 00 00 00 00 00 00 00 00 ..|............. 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace (crc 4401212): [<00000000e21852d0>] kmemleak_alloc+0x34/0x40 [<000000009c583f7b>] __kmalloc_cache_noprof+0x26c/0x2f4 [<0000000086e7dd64>] clk_hw_create_clk.part.0.isra.0+0x58/0x2f4 [<00000000dcf1ac31>] clk_hw_get_clk+0x8c/0x114 [<0000000063eb2c90>] clk_test_single_parent_mux_set_range_disjoint_child_last+0x3c/0xa0 [<00000000c97db55a>] kunit_try_run_case+0x13c/0x3ac [<0000000026b41f03>] kunit_generic_run_threadfn_adapter+0x80/0xec [<0000000066619fb8>] kthread+0x2e8/0x374 [<00000000a1157f53>] ret_from_fork+0x10/0x20 ...... Fixes: 02cdeace1e1e ("clk: tests: Add tests for single parent mux") Fixes: 2e9cad1abc71 ("clk: tests: Add some tests for orphan with multiple parents") Fixes: 433fb8a611ca ("clk: tests: Add missing test case for ranges") Signed-off-by: Jinjie Ruan Link: https://lore.kernel.org/r/20241016022658.2131826-1-ruanjinjie@huawei.com Reviewed-by: Maxime Ripard Signed-off-by: Stephen Boyd

clk: test: Add KUnit tests for clock-assigned-rates{-u64} DT properties

2024-10-09T23:25:32+00:00

Add unit tests for the two types of assigned rate properties. Test different combinations of assigned clocks and make sure that rates aren't assigned when the DT properties are malformed or are zero. Cc: Peng Fan Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240822002433.1163814-4-sboyd@kernel.org

clk: Add KUnit tests for clks registered with struct clk_parent_data

2024-07-29T22:33:13+00:00

Test that clks registered with 'struct clk_parent_data' work as intended and can find their parents. Cc: Christian Marangi Cc: Brendan Higgins Reviewed-by: David Gow Cc: Rae Moar Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240718210513.3801024-9-sboyd@kernel.org

clk: test: add missing MODULE_DESCRIPTION() macros

2024-06-03T22:46:46+00:00

make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/clk_test.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/clk-gate_test.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/clk-fractional-divider_test.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson Link: https://lore.kernel.org/r/20240602-md-clk-test-v1-1-a6afd4793337@quicinc.com [sboyd@kernel.org: Reword header and description] Signed-off-by: Stephen Boyd