<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/clk/bcm, branch v4.11.5</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v4.11.5</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v4.11.5'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2017-01-21T00:22:56+00:00</updated>
<entry>
<title>clk: bcm2835: Add leaf clock measurement support, disabled by default</title>
<updated>2017-01-21T00:22:56+00:00</updated>
<author>
<name>Eric Anholt</name>
<email>eric@anholt.net</email>
</author>
<published>2017-01-17T20:31:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3f9195811d8d829556c4cd88d3f9e56a80d5ba60'/>
<id>urn:sha1:3f9195811d8d829556c4cd88d3f9e56a80d5ba60</id>
<content type='text'>
This proved incredibly useful during debugging of the DSI driver, to
see if our clocks were running at rate we requested.  Let's leave it
here for the next person interacting with clocks on the platform (and
so that hopefully we can just hook it up to debugfs some day).

Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm2835: Register the DSI0/DSI1 pixel clocks.</title>
<updated>2017-01-21T00:22:55+00:00</updated>
<author>
<name>Eric Anholt</name>
<email>eric@anholt.net</email>
</author>
<published>2017-01-17T20:31:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8a39e9fa578229fd4604266c6ebb1a3a77d7994c'/>
<id>urn:sha1:8a39e9fa578229fd4604266c6ebb1a3a77d7994c</id>
<content type='text'>
The DSI pixel clocks are muxed from clocks generated in the analog phy
by the DSI driver.  In order to set them as parents, we need to do the
same name lookup dance on them as we do for our root oscillator.

Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.</title>
<updated>2017-01-21T00:22:54+00:00</updated>
<author>
<name>Eric Anholt</name>
<email>eric@anholt.net</email>
</author>
<published>2017-01-17T20:31:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=55486091bd1e1c5ed28c43c0d6b3392468a9adb5'/>
<id>urn:sha1:55486091bd1e1c5ed28c43c0d6b3392468a9adb5</id>
<content type='text'>
Our core PLLs are intended to be configured once and left alone.  With
the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
change PLLD just to get closer to the requested DSI clock, thus
changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
it, and breaking ethernet.

We *do* want PLLH to change so that PLLH_AUX can be exactly the value
we want, though.  Thus, we need to have a per-divider policy of
whether to pass rate changes up.

Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate()</title>
<updated>2016-12-12T19:25:40+00:00</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@free-electrons.com</email>
</author>
<published>2016-12-12T08:00:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2aab7a2055a1705c9e30920d95a596226999eb21'/>
<id>urn:sha1:2aab7a2055a1705c9e30920d95a596226999eb21</id>
<content type='text'>
best_rate is reported as potentially uninitialized by gcc.

Signed-off-by: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Fixes: 155e8b3b0ee3 ("clk: bcm: Support rate change propagation on bcm2835 clocks")
Reported-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Reviewed-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm: Make COMMON_CLK_IPROC into a library</title>
<updated>2016-12-09T00:29:35+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2016-11-23T22:41:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=100edfe33a313f2d076a5edf4b105eeb6137ab9a'/>
<id>urn:sha1:100edfe33a313f2d076a5edf4b105eeb6137ab9a</id>
<content type='text'>
The broadcom clk driver Kconfig file selects and depends on the
COMMON_CLK_IPROC config for different SoC specific drivers. Let's
simplify this by always selecting the COMMON_CLK_IPROC config,
turning it into a set of library code. We still want to retain
the SoC specific options, so we leave those in place. Since we're
here we also drop COMMON_CLK dependency because that's implicitly
handled by including this file in drivers/clk/Kconfig in the
right place and also make CLK_BCM_KONA default to y on the
architecture it exists for instead of plain default y.

Cc: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Cc: Ray Jui &lt;ray.jui@broadcom.com&gt;
Cc: Jon Mason &lt;jonmason@broadcom.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock</title>
<updated>2016-12-08T23:06:18+00:00</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@free-electrons.com</email>
</author>
<published>2016-12-01T21:00:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d86d46af84855403c00018be1c3e7bc190f2a6cd'/>
<id>urn:sha1:d86d46af84855403c00018be1c3e7bc190f2a6cd</id>
<content type='text'>
The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).

Signed-off-by: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Reviewed-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm: Support rate change propagation on bcm2835 clocks</title>
<updated>2016-12-08T23:06:08+00:00</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@free-electrons.com</email>
</author>
<published>2016-12-01T21:00:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=155e8b3b0ee320ae866b97dd31eba8a1f080a772'/>
<id>urn:sha1:155e8b3b0ee320ae866b97dd31eba8a1f080a772</id>
<content type='text'>
Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set
to a precise rate (in our case 108MHz). With the current implementation,
where peripheral clocks are not allowed to forward rate change requests
to their parents, it is impossible to match this requirement unless the
bootloader has configured things correctly, or a specific rate has been
assigned through the DT (with the assigned-clk-rates property).

Add a new field to struct bcm2835_clock_data to specify which parent
clocks accept rate change propagation, and support set rate propagation
in bcm2835_clock_determine_rate().

Signed-off-by: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Reviewed-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk</title>
<updated>2016-12-08T22:55:04+00:00</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@free-electrons.com</email>
</author>
<published>2016-12-01T19:27:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=68af4fa8f39b542a6cde7ac19518d88e9b3099dc'/>
<id>urn:sha1:68af4fa8f39b542a6cde7ac19518d88e9b3099dc</id>
<content type='text'>
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.

Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.

Signed-off-by: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: &lt;stable@vger.kernel.org&gt;
Reviewed-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'clk-fixes' into clk-next</title>
<updated>2016-11-23T22:31:45+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2016-11-23T22:31:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5e2035b90e7192b48f9615ddfbcc6fef1149ed8a'/>
<id>urn:sha1:5e2035b90e7192b48f9615ddfbcc6fef1149ed8a</id>
<content type='text'>
* clk-fixes:
  clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX
  clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
  clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
</content>
</entry>
<entry>
<title>clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX</title>
<updated>2016-11-23T22:31:11+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2016-11-22T17:43:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b7d79eb4615e3eb5947355f7b4354818cba037f7'/>
<id>urn:sha1:b7d79eb4615e3eb5947355f7b4354818cba037f7</id>
<content type='text'>
With commit f4e871509959 ("clk: iproc: Make clocks visible options"),
COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX
also selects that option, this causes the following Kconfig warning:

warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct
dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) &amp;&amp; COMMON_CLK)

Fix this by adding proper depends for COMMON_CLK_IPROC

Fixes: f4e871509959 ("clk: iproc: Make clocks visible options")
Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Reviewed-by: Ray Jui &lt;ray.jui@broadcom.com&gt;
[sboyd@codeaurora.org: Drop default part as it's redundant]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
