kernel/linux.git/drivers/clk/at91, branch v6.6.134

clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register

2025-11-24T09:29:48+00:00

[ Upstream commit af98caeaa7b6ad11eb7b7c8bfaddc769df2889f3 ] This register is important for sequencing the commands to PLLs, so actually write the update bits with regmap_write_bits() instead of relying on a read/modify/write regmap command that could skip the actual hardware write if the value is identical to the one read. It's changed when modification is needed to the PLL, when read-only operation is done, we could keep the call to regmap_update_bits(). Add a comment to the sam9x60_div_pll_set_div() function that uses this PLL_UPDT register so that it's used consistently, according to the product's datasheet. Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner # on sama7d65 and sam9x75 Link: https://lore.kernel.org/r/20250827150811.82496-1-nicolas.ferre@microchip.com [claudiu.beznea: fix "Alignment should match open parenthesis" checkpatch.pl check] Signed-off-by: Claudiu Beznea Signed-off-by: Sasha Levin

clk: at91: clk-master: Add check for divide by 3

2025-11-24T09:29:48+00:00

[ Upstream commit e0237f5635727d64635ec6665e1de9f4cacce35c ] A potential divider for the master clock is div/3. The register configuration for div/3 is MASTER_PRES_MAX. The current bit shifting method does not work for this case. Checking for MASTER_PRES_MAX will ensure the correct decimal value is stored in the system. Signed-off-by: Ryan Wanner Signed-off-by: Nicolas Ferre Signed-off-by: Sasha Levin

clk: at91: peripheral: fix return value

2025-10-19T14:30:40+00:00

[ Upstream commit 47b13635dabc14f1c2fdcaa5468b47ddadbdd1b5 ] determine_rate() is expected to return an error code, or 0 on success. clk_sam9x5_peripheral_determine_rate() has a branch that returns the parent rate on a certain case. This is the behavior of round_rate(), so let's go ahead and fix this by setting req->rate. Fixes: b4c115c76184f ("clk: at91: clk-peripheral: add support for changeable parent rate") Reviewed-by: Alexander Sverdlin Acked-by: Nicolas Ferre Signed-off-by: Brian Masney Signed-off-by: Sasha Levin

clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs

2024-10-04T14:29:30+00:00

[ Upstream commit 2d6e9ee7cb3e79b1713783c633b13af9aeffc90c ] The maximum number of PLL components on SAMA7G5 is 3 (one fractional part and 2 dividers). Allocate the needed amount of memory for sama7g5_plls 2d array. Previous code used to allocate 7 array entries for each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which parses the sama7g5_plls 2d array. Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea Signed-off-by: Sasha Levin

Merge branches 'clk-qcom' and 'clk-microchip' into clk-next

2023-06-26T23:36:14+00:00

* clk-qcom: (63 commits) clk: qcom: gcc-sc8280xp: Add runtime PM clk: qcom: gpucc-sc8280xp: Add runtime PM clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags clk: qcom: gpucc-sm6375: Enable runtime pm dt-bindings: clock: sm6375-gpucc: Add VDD_GX clk: qcom: gcc-sm6115: Add missing PLL config properties clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) clk: qcom: gcc-ipq6018: remove duplicate initializers clk: qcom: gcc-ipq9574: Enable crypto clocks dt-bindings: clock: Add crypto clock and reset definitions clk: qcom: Add lpass audio clock controller driver for SC8280XP clk: qcom: Add lpass clock controller driver for SC8280XP dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226 clk: qcom: gpucc-sm8550: Add support for graphics clock controller clk: qcom: Add support for SM8450 GPUCC clk: qcom: gcc-sm8450: Enable hw_clk_ctrl clk: qcom: rcg2: Make hw_clk_ctrl toggleable dt-bindings: clock: qcom: Add SM8550 graphics clock controller ... * clk-microchip: clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id clk: at91: sama7g5: switch to parent_hw and parent_data clk: at91: sckc: switch to parent_data/parent_hw clk: at91: clk-sam9x60-pll: add support for parent_hw clk: at91: clk-utmi: add support for parent_hw clk: at91: clk-system: add support for parent_hw clk: at91: clk-programmable: add support for parent_hw clk: at91: clk-peripheral: add support for parent_hw clk: at91: clk-master: add support for parent_hw clk: at91: clk-generated: add support for parent_hw clk: at91: clk-main: add support for parent_data/parent_hw

clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id

2023-06-21T07:42:48+00:00

s/ep_chg_chg_id/ep_chg_id in documentation of master clock structure. Signed-off-by: Claudiu Beznea Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20230615093227.576102-12-claudiu.beznea@microchip.com

clk: at91: sama7g5: switch to parent_hw and parent_data

2023-06-21T07:42:48+00:00

Switch SAMA7G5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Extra time saved on registration is ~250us when running at 800MHz. Signed-off-by: Claudiu Beznea Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20230615093227.576102-11-claudiu.beznea@microchip.com

clk: at91: sckc: switch to parent_data/parent_hw

2023-06-21T07:42:48+00:00

Switch slow clock drivers to use parent_data and parent_hw. With this parent-child relation is described with pointers rather than strings. Signed-off-by: Claudiu Beznea Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20230615093227.576102-10-claudiu.beznea@microchip.com

clk: at91: clk-sam9x60-pll: add support for parent_hw

2023-06-21T07:42:48+00:00

Add support for parent_hw in SAM9X60 PLL clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-sam9x60-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20230615093227.576102-9-claudiu.beznea@microchip.com

clk: at91: clk-utmi: add support for parent_hw

2023-06-21T07:42:48+00:00

Add support for parent_hw in utmi clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-utmi were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20230615093227.576102-8-claudiu.beznea@microchip.com