kernel/linux.git/drivers/clk/Makefile, branch v6.12.80

clk: keystone: fix compile testing

2025-12-18T12:55:13+00:00

[ Upstream commit b276445e98fe28609688fb85b89a81b803910e63 ] Some keystone clock drivers can be selected when COMPILE_TEST is enabled but since commit b745c0794e2f ("clk: keystone: Add sci-clk driver support") they are never actually built. Enable compile testing by allowing the build system to process the keystone drivers. Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Signed-off-by: Johan Hovold Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2024-09-26T19:00:25+00:00

Pull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/" * tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ...

clk: ep93xx: add DT support for Cirrus EP93xx

2024-09-12T14:33:10+00:00

Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c trying to do everything the device tree way: - provide clock acces via of - drop clk_hw_register_clkdev - drop init code and use module_auxiliary_driver Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin Signed-off-by: Arnd Bergmann

clk: Add KUnit tests for clks registered with struct clk_parent_data

2024-07-29T22:33:13+00:00

Test that clks registered with 'struct clk_parent_data' work as intended and can find their parents. Cc: Christian Marangi Cc: Brendan Higgins Reviewed-by: David Gow Cc: Rae Moar Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240718210513.3801024-9-sboyd@kernel.org

clk: Add KUnit tests for clk fixed rate basic type

2024-07-29T22:33:13+00:00

Test that the fixed rate basic type clk works as intended. Cc: Brendan Higgins Cc: David Gow Cc: Rae Moar Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240718210513.3801024-8-sboyd@kernel.org

clk: Add test managed clk provider/consumer APIs

2024-07-29T22:33:12+00:00

Unit tests are more ergonomic and simpler to understand if they don't have to hoist a bunch of code into the test harness init and exit functions. Add some test managed wrappers for the clk APIs so that clk unit tests can write more code in the actual test and less code in the harness. Only add APIs that are used for now. More wrappers can be added in the future as necessary. Cc: Brendan Higgins Cc: David Gow Cc: Rae Moar Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240718210513.3801024-7-sboyd@kernel.org

clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks

2024-07-15T19:15:01+00:00

Add support for the AP sub-system clock controller in the T-Head TH1520. This include CPU, DPU, GMAC and TEE PLLs. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li Signed-off-by: Yangtao Li Co-developed-by: Jisheng Zhang Signed-off-by: Jisheng Zhang Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs Signed-off-by: Drew Fustini Link: https://lore.kernel.org/r/20240711-th1520-clk-v3-2-6ff17bb318fb@tenstorrent.com Signed-off-by: Stephen Boyd

clk: sophgo: Add clock support for CV1800 SoC

2024-04-11T07:02:20+00:00

Add clock definition and driver code for CV1800 SoC. Signed-off-by: Inochi Amaoto Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsx Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Link: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd

clk: stm32mp1: move stm32mp1 clock driver into stm32 directory

2023-12-17T23:33:26+00:00

Move all STM32MP clock drivers into same directory (stm32). Signed-off-by: Gabriel Fernandez Link: https://lore.kernel.org/r/20231208143700.354785-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd

Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and 'clk-frac-divider' into clk-next

2023-10-30T21:12:20+00:00

- Make clk kunit tests work with lockdep - Fix clk gate kunit test for big-endian - Convert more than a handful of clk drivers to use regmap maple tree - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk implementation * clk-renesas: (23 commits) clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() clk: renesas: Add minimal boot support for RZ/G3S SoC clk: renesas: rzg2l: Add divider clock for RZ/G3S clk: renesas: rzg2l: Refactor SD mux driver clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: Add struct clk_hw_data clk: renesas: rzg2l: Add support for RZ/G3S PLL clk: renesas: rzg2l: Remove critical area clk: renesas: rzg2l: Fix computation formula clk: renesas: rzg2l: Trust value returned by hardware clk: renesas: rzg2l: Lock around writes to mux register clk: renesas: rzg2l: Wait for status bit of SD mux before continuing clk: renesas: rcar-gen3: Extend SDnH divider table dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC clk: renesas: r8a7795: Constify r8a7795_*_clks clk: renesas: r9a06g032: Name anonymous structs clk: renesas: r9a06g032: Fix kerneldoc warning clk: renesas: rzg2l: Use u32 for flag and mux_flags clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields ... * clk-kunit: clk: Fix clk gate kunit test on big-endian CPUs clk: Parameterize clk_leaf_mux_set_rate_parent clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops * clk-regmap: clk: versaclock7: Convert to use maple tree register cache clk: versaclock5: Convert to use maple tree register cache clk: versaclock3: Convert to use maple tree register cache clk: versaclock3: Remove redundant _is_writeable() clk: si570: Convert to use maple tree register cache clk: si544: Convert to use maple tree register cache clk: si5351: Convert to use maple tree register cache clk: si5341: Convert to use maple tree register cache clk: si514: Convert to use maple tree register cache clk: cdce925: Convert to use maple tree register cache * clk-frac-divider: clk: fractional-divider: tests: Add test suite for edge cases clk: fractional-divider: Improve approximation when zero based and export