kernel/linux.git/drivers/cache, branch v6.19.11

cache: ax45mp: Fix device node reference leak in ax45mp_cache_init()

2026-03-25T10:13:23+00:00

[ Upstream commit 0528a348b04b327a4611e29589beb4c9ae81304a ] In ax45mp_cache_init(), of_find_matching_node() returns a device node with an incremented reference count that must be released with of_node_put(). The current code fails to call of_node_put() which causes a reference leak. Use the __free(device_node) attribute to ensure automatic cleanup when the variable goes out of scope. Fixes: d34599bcd2e4 ("cache: Add L2 cache management for Andes AX45MP RISC-V core") Signed-off-by: Felix Gu Signed-off-by: Conor Dooley Signed-off-by: Sasha Levin

cache: starfive: fix device node leak in starlink_cache_init()

2026-03-25T10:13:23+00:00

[ Upstream commit 3c85234b979af71cb9db5eb976ea08a468415767 ] of_find_matching_node() returns a device_node with refcount incremented. Use __free(device_node) attribute to automatically call of_node_put() when the variable goes out of scope, preventing the refcount leak. Fixes: cabff60ca77d ("cache: Add StarFive StarLink cache management") Signed-off-by: Felix Gu Reviewed-by: Jonathan Cameron Signed-off-by: Conor Dooley Signed-off-by: Sasha Levin

cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent

2025-11-21T18:42:02+00:00

Hydra Home Agent is a device used to maintain cache coherency. Add support for explicit cache maintenance operations using it. A system has multiple of these agents. Whilst only one agent is responsible for a given cache line, interleave means that for a range operation, responsibility for the cache lines making up the range will typically be spread across multiple instances. Put this driver on a new Kconfig menu under drivers/cache. The short description as memory hotplug like operations is intended to cover the somewhat complex set of cases where this unit applies and differentiate it clearly from typical non coherent DMA flows. Co-developed-by: Yicong Yang Signed-off-by: Yicong Yang Signed-off-by: Yushan Wang Signed-off-by: Jonathan Cameron Signed-off-by: Conor Dooley

cache: Make top level Kconfig menu a boolean dependent on RISCV

2025-11-21T18:42:02+00:00

The next patch will add a new type of cache maintenance driver responsible for flushing deeper than is necessary for non coherent DMA (current use case of drivers/cache drivers), as needed when performing operations such as memory hotplug and security unlocking of persistent memory. The two types of operation are similar enough to share a drivers/cache directory and MAINTAINERS but are otherwise currently unrelated. To avoid confusion have two separate menus. Each has dependencies that are implemented by making them boolean symbols, here CACHEMAINT_FOR_DMA which is dependent on RISCV as all driver are currently for platforms of that architecture. Set new symbol default to y to avoid breaking existing configs. This has no affect on actual code built, just visibility of the menu. Suggested-by: Arnd Bergmann Signed-off-by: Jonathan Cameron Signed-off-by: Conor Dooley

cache: sifive_ccache: Optimize cache flushes

2025-09-11T18:13:21+00:00

Fence instructions are required only at the beginning and the end of a flush operation, not separately for each cache line being flushed. Speed up cache flushes by about 15% by removing the extra fences. Signed-off-by: Samuel Holland Signed-off-by: Conor Dooley

cache: sifive_ccache: Add ESWIN EIC7700 support

2025-04-07T15:53:46+00:00

This adds support for the ESWIN EIC7700 SoC which also features this SiFive composable cache controller. Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland Signed-off-by: Conor Dooley

cache: StarFive: Require a 64-bit system

2024-08-01T14:15:02+00:00

This has a bunch of {read,write}q() calls, so it won't work on 32-bit systems. I don't think there's any 32-bit StarFive systems, so for now just require 64-bit. Fixes: cabff60ca77d ("cache: Add StarFive StarLink cache management") Acked-by: Conor Dooley Reviewed-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20240722154519.25375-2-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt

cache: Add StarFive StarLink cache management

2024-05-28T11:34:11+00:00

Add StarFive Starlink cache management driver. The driver enables RISC-V non-standard cache operation on SoC that does not support Zicbom extension instructions. Signed-off-by: Joshua Yeong Signed-off-by: Conor Dooley

cache: sifive_ccache: Silence unused variable warning

2024-04-11T06:28:37+00:00

With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns: drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init': drivers/cache/sifive_ccache.c:293:23: warning: variable 'quirks' set but not used [-Wunused-but-set-variable] 293 | unsigned long quirks; | ^~~~~~ This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk still handled in this function. Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202403311253.Z4NvIBxI-lkp@intel.com/ Signed-off-by: Samuel Holland Signed-off-by: Conor Dooley

cache: sifive_ccache: Partially convert to a platform driver

2024-03-28T22:40:56+00:00

Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") broke ccache initialization because the PLIC IRQ domain is no longer available during an arch_initcall: [ 0.087229] irq: no irq domain found for interrupt-controller@c000000 ! [ 0.087255] CCACHE: Could not request IRQ 0 Fix this by moving the IRQ handling code to a platform driver. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Samuel Holland Tested-by: Geert Uytterhoeven Signed-off-by: Conor Dooley