kernel/linux.git/drivers/cache/sifive_ccache.c, branch v6.19.11Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.112025-09-11T18:13:21+00:00cache: sifive_ccache: Optimize cache flushes2025-09-11T18:13:21+00:00Samuel Hollandsamuel.holland@sifive.com2025-09-09T22:41:27+00:00urn:sha1:941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0
Fence instructions are required only at the beginning and the end of
a flush operation, not separately for each cache line being flushed.
Speed up cache flushes by about 15% by removing the extra fences.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
cache: sifive_ccache: Add ESWIN EIC7700 support2025-04-07T15:53:46+00:00Pinkesh Vaghelapinkesh.vaghela@einfochips.com2025-03-20T10:54:45+00:00urn:sha1:82e8c6931074e1fa1bdbdcc01604e164c42f989e
This adds support for the ESWIN EIC7700 SoC which also features this
SiFive composable cache controller.
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
cache: sifive_ccache: Silence unused variable warning2024-04-11T06:28:37+00:00Samuel Hollandsamuel.holland@sifive.com2024-04-10T23:22:03+00:00urn:sha1:6b0856ee585d7f8a544546c3c5f1f4c49162e451
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init':
drivers/cache/sifive_ccache.c:293:23: warning: variable 'quirks' set but not used [-Wunused-but-set-variable]
293 | unsigned long quirks;
| ^~~~~~
This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk
still handled in this function.
Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202403311253.Z4NvIBxI-lkp@intel.com/
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
cache: sifive_ccache: Partially convert to a platform driver2024-03-28T22:40:56+00:00Samuel Hollandsamuel.holland@sifive.com2024-03-27T05:45:24+00:00urn:sha1:c90847bcbfb65d0f1c48fcc73a2b3a2d4ceac6a1
Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a
platform driver") broke ccache initialization because the PLIC IRQ
domain is no longer available during an arch_initcall:
[ 0.087229] irq: no irq domain found for interrupt-controller@c000000 !
[ 0.087255] CCACHE: Could not request IRQ 0
Fix this by moving the IRQ handling code to a platform driver.
Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
soc: sifive: ccache: Add StarFive JH7100 support2023-11-22T11:58:14+00:00Emil Renner Berthingkernel@esmil.dk2023-10-31T14:14:44+00:00urn:sha1:0d5701dc9cd653ae757cc06e39b3a39272863395
This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
exension, so instead we need to use this cache controller for
non-standard cache management operations.
Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
soc: sifive: shunt ccache driver to drivers/cache2023-11-22T11:49:25+00:00Conor Dooleyconor.dooley@microchip.com2023-10-12T09:22:09+00:00urn:sha1:971f128bb2d9314203d365b7f163a5c35167bb6b
Move the ccache driver over to drivers/cache, out of the drivers/soc
dumping ground, to this new collection point for cache controller
drivers.
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>