kernel/linux.git/arch/xtensa/include/asm/core.h, branch v6.6.134Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.1342023-09-20T11:56:41+00:00xtensa: add default definition for XCHAL_HAVE_DIV322023-09-20T11:56:41+00:00Max Filippovjcmvbkbc@gmail.com2023-09-20T11:15:22+00:00urn:sha1:494e87ffa0159b3f879694a9231089707792a44d
When variant FSF is set, XCHAL_HAVE_DIV32 is not defined. Add default
definition for that macro to prevent build warnings:
arch/xtensa/lib/divsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32
arch/xtensa/lib/modsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32
Fixes: 173d6681380a ("xtensa: remove extra header files")
Suggested-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: lore.kernel.org/r/202309150556.t0yCdv3g-lkp@intel.com
xtensa: PMU: fix base address for the newer hardware2023-08-28T02:22:56+00:00Max Filippovjcmvbkbc@gmail.com2023-07-24T07:58:24+00:00urn:sha1:687eb3c42f4ad81e7c947c50e2d865f692064291
With introduction of ERI access control in RG.0 base address of the PMU
unit registers has changed. Add support for the new PMU configuration.
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: report trax and perf counters in cpuinfo2023-06-13T02:48:57+00:00Max Filippovjcmvbkbc@gmail.com2023-05-21T20:50:20+00:00urn:sha1:e6807b44e49aa737b4ee9fb614da3152e2ce49c0
Add 'trax' to the list of CPU features when xtensa core is configured
with TRAX.
Add 'perf' to the list of CPU features when xtensa core is configured
with perf counters and show the number of configured perf counters.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: merge stack alignment definitions2022-03-19T20:08:11+00:00Max Filippovjcmvbkbc@gmail.com2022-03-19T18:06:30+00:00urn:sha1:e94dc6bbdf29787a5ddb01c143a074c31e427dc7
xtensa currently has two different definitions for stack alignment.
Replace it with single definition usable in both C and assembly.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: definitions for call0 ABI2021-10-19T05:19:34+00:00Max Filippovjcmvbkbc@gmail.com2021-05-01T22:30:06+00:00urn:sha1:5cce39b6aaa02da77e071b2b0880bedfb903330f
Add assembly macros for calls, call arguments, preserved registers,
function entry and return for windowed and call0 ABIs.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: clean up optional XCHAL_* definitions2020-02-01T08:43:28+00:00Max Filippovjcmvbkbc@gmail.com2020-02-01T05:20:58+00:00urn:sha1:a922b1561137fc516e7c77c478779f7d198cc9cf
Simplify users of XCHAL_HAVE_EXTERN_REGS and XCHAL_HAVE_VECBASE and
always define them as 0 if they're not defined in the variant/core.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: implement initialize_cacheattr for MPU cores2019-05-07T17:36:34+00:00Max Filippovjcmvbkbc@gmail.com2019-05-06T23:47:41+00:00urn:sha1:a5944195d00a359e28d6e093593609bcee37ed5e
Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add exclusive atomics support2019-05-07T17:36:31+00:00Max Filippovjcmvbkbc@gmail.com2018-12-21T01:18:12+00:00urn:sha1:f7c34874f04a80d6c39a32f08da2529e59602d3c
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: replace variant/core.h with asm/core.h2019-05-07T00:48:55+00:00Max Filippovjcmvbkbc@gmail.com2019-01-02T03:41:55+00:00urn:sha1:8f8d5745bb520c76b81abef4a2cb3023d0313bfd
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>