kernel/linux.git/arch/xtensa/include/asm/core.h, branch v5.15.212Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.15.2122023-10-06T11:18:13+00:00xtensa: add default definition for XCHAL_HAVE_DIV322023-10-06T11:18:13+00:00Max Filippovjcmvbkbc@gmail.com2023-09-20T11:15:22+00:00urn:sha1:8e0f78a84f64d8e6de9fc3c7a5989b119cfdaf01
[ Upstream commit 494e87ffa0159b3f879694a9231089707792a44d ]
When variant FSF is set, XCHAL_HAVE_DIV32 is not defined. Add default
definition for that macro to prevent build warnings:
arch/xtensa/lib/divsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32
arch/xtensa/lib/modsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32
Fixes: 173d6681380a ("xtensa: remove extra header files")
Suggested-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: lore.kernel.org/r/202309150556.t0yCdv3g-lkp@intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
xtensa: PMU: fix base address for the newer hardware2023-09-19T10:22:51+00:00Max Filippovjcmvbkbc@gmail.com2023-07-24T07:58:24+00:00urn:sha1:a905ac21b2abe275b17bac612fb482e98eb81124
commit 687eb3c42f4ad81e7c947c50e2d865f692064291 upstream.
With introduction of ERI access control in RG.0 base address of the PMU
unit registers has changed. Add support for the new PMU configuration.
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
xtensa: clean up optional XCHAL_* definitions2020-02-01T08:43:28+00:00Max Filippovjcmvbkbc@gmail.com2020-02-01T05:20:58+00:00urn:sha1:a922b1561137fc516e7c77c478779f7d198cc9cf
Simplify users of XCHAL_HAVE_EXTERN_REGS and XCHAL_HAVE_VECBASE and
always define them as 0 if they're not defined in the variant/core.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: implement initialize_cacheattr for MPU cores2019-05-07T17:36:34+00:00Max Filippovjcmvbkbc@gmail.com2019-05-06T23:47:41+00:00urn:sha1:a5944195d00a359e28d6e093593609bcee37ed5e
Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add exclusive atomics support2019-05-07T17:36:31+00:00Max Filippovjcmvbkbc@gmail.com2018-12-21T01:18:12+00:00urn:sha1:f7c34874f04a80d6c39a32f08da2529e59602d3c
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: replace variant/core.h with asm/core.h2019-05-07T00:48:55+00:00Max Filippovjcmvbkbc@gmail.com2019-01-02T03:41:55+00:00urn:sha1:8f8d5745bb520c76b81abef4a2cb3023d0313bfd
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>