kernel/linux.git/arch/xtensa/include/asm/cacheasm.h, branch v6.6.132Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.1322018-08-14T03:08:01+00:00xtensa: increase ranges in ___invalidate_{i,d}cache_all2018-08-14T03:08:01+00:00Max Filippovjcmvbkbc@gmail.com2018-08-11T05:21:22+00:00urn:sha1:fec3259c9f747c039f90e99570540114c8d81a14
Cache invalidation macros use cache line size to iterate over
invalidated cache lines, assuming that all cache ways are invalidated by
single instruction, but xtensa ISA recommends to not assume that for
future compatibility:
In some implementations all ways at index Addry-1..z are invalidated
regardless of the specified way, but for future compatibility this
behavior should not be assumed.
Iterate over all cache ways in ___invalidate_icache_all and
___invalidate_dcache_all.
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: limit offsets in __loop_cache_{all,page}2018-08-14T03:07:54+00:00Max Filippovjcmvbkbc@gmail.com2018-08-11T03:43:48+00:00urn:sha1:be75de25251f7cf3e399ca1f584716a95510d24a
When building kernel for xtensa cores with big cache lines (e.g. 128
bytes or more) __loop_cache_all and __loop_cache_page may generate
assembly instructions with immediate fields that are too big. This
results in the following build errors:
arch/xtensa/mm/misc.S: Assembler messages:
arch/xtensa/mm/misc.S:464: Error: operand 2 of 'diwbi' has invalid value '256'
arch/xtensa/mm/misc.S:464: Error: operand 2 of 'diwbi' has invalid value '384'
arch/xtensa/kernel/head.S: Assembler messages:
arch/xtensa/kernel/head.S:172: Error: operand 2 of 'diu' has invalid value '256'
arch/xtensa/kernel/head.S:172: Error: operand 2 of 'diu' has invalid value '384'
arch/xtensa/kernel/head.S:176: Error: operand 2 of 'iiu' has invalid value '256'
arch/xtensa/kernel/head.S:176: Error: operand 2 of 'iiu' has invalid value '384'
arch/xtensa/kernel/head.S:255: Error: operand 2 of 'diwb' has invalid value '256'
arch/xtensa/kernel/head.S:255: Error: operand 2 of 'diwb' has invalid value '384'
Add parameter max_immed to these macros and use it to limit values of
immediate operands. Extract common code of these macros into the new
macro __loop_cache_unroll.
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: define ___unlock_[di]cache_all unconditionally2016-06-29T01:18:45+00:00Max Filippovjcmvbkbc@gmail.com2016-06-29T01:18:45+00:00urn:sha1:8a5043b68320aa880d46744ab40915bee8939882
Provide macro definitions regardless of whether caches are lockable or
not, make definitions empty in latter case.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: fix build for configs without cache options2015-11-02T15:02:51+00:00Max Filippovjcmvbkbc@gmail.com2015-09-24T20:20:46+00:00urn:sha1:01618bded680573163403666d0546be536b22ac0
- make cache-related assembly macros empty if core doesn't have
corresponding cache type;
- don't initialize cache attributes in instruction/data TLB entries if
there's no corresponding cache type.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: clean up files to make them code-style compliant2012-12-19T05:10:25+00:00Chris Zankelchris@zankel.net2012-11-29T00:53:51+00:00urn:sha1:c4c4594b005d89b56964071bbbdeb07daac5bc76
Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.
Signed-off-by: Chris Zankel <chris@zankel.net>
xtensa: move headers files to arch/xtensa/include2008-11-06T18:25:09+00:00Chris Zankelchris@zankel.net2008-11-06T14:40:46+00:00urn:sha1:367b8112fe2ea5c39a7bb4d263dcdd9b612fae18
Move all header files for xtensa to arch/xtensa/include and platform and
variant header files to the appropriate arch/xtensa/platforms/ and
arch/xtensa/variants/ directories.
Moving the files gets also rid of all uses of symlinks in the Makefile.
This has been completed already for the majority of the architectures
and xtensa is one out of six missing.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Chris Zankel <chris@zankel.net>