kernel/linux.git/arch/sh/include/asm/cacheflush.h, branch v6.12.80

sh: cache: Move forward declarations to

2024-05-02T10:01:31+00:00

arch/sh/kernel/cpu/init.c:99:29: warning: no previous prototype for 'l2_cache_init' [-Wmissing-prototypes] arch/sh/kernel/cpu/sh4a/setup-sh7723.c:422:6: warning: no previous prototype for 'l2_cache_init' [-Wmissing-prototypes] arch/sh/kernel/cpu/sh4a/setup-sh7724.c:842:6: warning: no previous prototype for 'l2_cache_init' [-Wmissing-prototypes] arch/sh/mm/cache-j2.c:48:13: warning: no previous prototype for 'j2_cache_init' [-Wmissing-prototypes] arch/sh/mm/cache-sh2.c:85:13: warning: no previous prototype for 'sh2_cache_init' [-Wmissing-prototypes] arch/sh/mm/cache-sh2a.c:181:13: warning: no previous prototype for 'sh2a_cache_init' [-Wmissing-prototypes] arch/sh/mm/cache-sh3.c:90:13: warning: no previous prototype for 'sh3_cache_init' [-Wmissing-prototypes] arch/sh/mm/cache-sh4.c:384:13: warning: no previous prototype for 'sh4_cache_init' [-Wmissing-prototypes] arch/sh/mm/cache-shx3.c:18:13: warning: no previous prototype for 'shx3_cache_init' [-Wmissing-prototypes] arch/sh/mm/flush-sh4.c:106:13: warning: no previous prototype for 'sh4__flush_region_init' [-Wmissing-prototypes] arch/sh/mm/cache-sh7705.c:190:13: warning: no previous prototype for 'sh7705_cache_init' [-Wmissing-prototypes] Fix this by moving all cache-related forward declarations to , and by including the latter where needed. Signed-off-by: Geert Uytterhoeven Reviewed-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/f47ab87636d16db4c47bebe1bf62650045f61989.1709579038.git.geert+renesas@glider.be Signed-off-by: John Paul Adrian Glaubitz

mm: Introduce flush_cache_vmap_early()

2023-12-14T08:23:17+00:00

The pcpu setup when using the page allocator sets up a new vmalloc mapping very early in the boot process, so early that it cannot use the flush_cache_vmap() function which may depend on structures not yet initialized (for example in riscv, we currently send an IPI to flush other cpus TLB). But on some architectures, we must call flush_cache_vmap(): for example, in riscv, some uarchs can cache invalid TLB entries so we need to flush the new established mapping to avoid taking an exception. So fix this by introducing a new function flush_cache_vmap_early() which is called right after setting the new page table entry and before accessing this new mapping. This new function implements a local flush tlb on riscv and is no-op for other architectures (same as today). Signed-off-by: Alexandre Ghiti Acked-by: Geert Uytterhoeven Signed-off-by: Dennis Zhou

mm: rationalise flush_icache_pages() and flush_icache_page()

2023-08-24T23:20:25+00:00

Move the default (no-op) implementation of flush_icache_pages() to from . Remove the flush_icache_page() wrapper from each architecture into . Link: https://lkml.kernel.org/r/20230802151406.3735276-32-willy@infradead.org Signed-off-by: Matthew Wilcox (Oracle) Signed-off-by: Andrew Morton

sh: implement the new page table range API

2023-08-24T23:20:23+00:00

Add PFN_PTE_SHIFT, update_mmu_cache_range(), flush_dcache_folio() and flush_icache_pages(). Change the PG_dcache_clean flag from being per-page to per-folio. Flush the entire folio containing the pages in flush_icache_pages() for ease of implementation. Link: https://lkml.kernel.org/r/20230802151406.3735276-25-willy@infradead.org Signed-off-by: Matthew Wilcox (Oracle) Acked-by: Mike Rapoport (IBM) Cc: Yoshinori Sato Cc: Rich Felker Cc: John Paul Adrian Glaubitz Signed-off-by: Andrew Morton

Add linux/cacheflush.h

2021-11-17T15:36:15+00:00

Many architectures do not include asm-generic/cacheflush.h, so turn the includes on their head and add linux/cacheflush.h which includes asm/cacheflush.h. Move the flush_dcache_folio() declaration from asm-generic/cacheflush.h to linux/cacheflush.h and change linux/highmem.h to include linux/cacheflush.h instead of asm/cacheflush.h so that all necessary places will see flush_dcache_folio(). More functions should have their default implementations moved in the future, but those are for follow-on patches. This fixes csky, sparc and sparc64 which were missed in the commit which added flush_dcache_folio(). Fixes: 08b0b0059bf1 ("mm: Add flush_dcache_folio()") Suggested-by: Christoph Hellwig Signed-off-by: Matthew Wilcox (Oracle) Acked-by: Geert Uytterhoeven

mm: Add flush_dcache_folio()

2021-10-18T11:49:36+00:00

This is a default implementation which calls flush_dcache_page() on each page in the folio. If architectures can do better, they should implement their own version of it. Signed-off-by: Matthew Wilcox (Oracle) Acked-by: Vlastimil Babka

mm: remove flush_kernel_dcache_page

2021-09-03T16:58:13+00:00

flush_kernel_dcache_page is a rather confusing interface that implements a subset of flush_dcache_page by not being able to properly handle page cache mapped pages. The only callers left are in the exec code as all other previous callers were incorrect as they could have dealt with page cache pages. Replace the calls to flush_kernel_dcache_page with calls to flush_dcache_page, which for all architectures does either exactly the same thing, can contains one or more of the following: 1) an optimization to defer the cache flush for page cache pages not mapped into userspace 2) additional flushing for mapped page cache pages if cache aliases are possible Link: https://lkml.kernel.org/r/20210712060928.4161649-7-hch@lst.de Signed-off-by: Christoph Hellwig Acked-by: Linus Torvalds Reviewed-by: Ira Weiny Cc: Alex Shi Cc: Geoff Levand Cc: Greentime Hu Cc: Guo Ren Cc: Helge Deller Cc: "James E.J. Bottomley" Cc: Nick Hu Cc: Paul Cercueil Cc: Rich Felker Cc: Russell King Cc: Thomas Bogendoerfer Cc: Ulf Hansson Cc: Vincent Chen Cc: Yoshinori Sato Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

sh: remove KERNEL ifdefs from non-UAPI headers

2020-08-15T02:05:14+00:00

There is no point in having __KERNEL__ ifdefs in headers not exported to userspace. Signed-off-by: Christoph Hellwig Signed-off-by: Rich Felker

sh: implement flush_icache_user_range

2020-06-08T18:05:58+00:00

The SuperH implementation of flush_icache_range seems to be able to cope with user addresses. Just define flush_icache_user_range to flush_icache_range. Signed-off-by: Christoph Hellwig Signed-off-by: Andrew Morton Cc: Yoshinori Sato Cc: Rich Felker Link: http://lkml.kernel.org/r/20200515143646.3857579-22-hch@lst.de Signed-off-by: Linus Torvalds

sh: introduce a sh_cacheop_vaddr helper

2018-08-02T11:54:06+00:00

And use it in the maple bus code to avoid a dma API dependency. Signed-off-by: Christoph Hellwig Acked-by: Yoshinori Sato