<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/arch/riscv/crypto, branch v6.12.80</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80'/>
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<updated>2026-01-08T09:14:55+00:00</updated>
<entry>
<title>lib/crypto: riscv/chacha: Avoid s0/fp register</title>
<updated>2026-01-08T09:14:55+00:00</updated>
<author>
<name>Vivian Wang</name>
<email>wangruikang@iscas.ac.cn</email>
</author>
<published>2025-12-29T22:37:29+00:00</published>
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<id>urn:sha1:7578200fa923409ac6400dad0ab6a675e3ccb867</id>
<content type='text'>
commit 43169328c7b4623b54b7713ec68479cebda5465f upstream.

In chacha_zvkb, avoid using the s0 register, which is the frame pointer,
by reallocating KEY0 to t5. This makes stack traces available if e.g. a
crash happens in chacha_zvkb.

No frame pointer maintenance is otherwise required since this is a leaf
function.

Signed-off-by: Vivian Wang &lt;wangruikang@iscas.ac.cn&gt;
Fixes: bb54668837a0 ("crypto: riscv - add vector crypto accelerated ChaCha20")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20251202-riscv-chacha_zvkb-fp-v2-1-7bd00098c9dc@iscas.ac.cn
Signed-off-by: Eric Biggers &lt;ebiggers@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>crypto: lib/Kconfig - Hide arch options from user</title>
<updated>2025-05-02T05:59:32+00:00</updated>
<author>
<name>Herbert Xu</name>
<email>herbert@gondor.apana.org.au</email>
</author>
<published>2025-02-27T07:48:39+00:00</published>
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<id>urn:sha1:67727c5764a8ff948b4e8e7e292aa622f981ce44</id>
<content type='text'>
commit 17ec3e71ba797cdb62164fea9532c81b60f47167 upstream.

The ARCH_MAY_HAVE patch missed arm64, mips and s390.  But it may
also lead to arch options being enabled but ineffective because
of modular/built-in conflicts.

As the primary user of all these options wireguard is selecting
the arch options anyway, make the same selections at the lib/crypto
option level and hide the arch options from the user.

Instead of selecting them centrally from lib/crypto, simply set
the default of each arch option as suggested by Eric Biggers.

Change the Crypto API generic algorithms to select the top-level
lib/crypto options instead of the generic one as otherwise there
is no way to enable the arch options (Eric Biggers).  Introduce a
set of INTERNAL options to work around dependency cycles on the
CONFIG_CRYPTO symbol.

Fixes: 1047e21aecdf ("crypto: lib/Kconfig - Fix lib built-in failure when arch is modular")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Reported-by: Arnd Bergmann &lt;arnd@kernel.org&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202502232152.JC84YDLp-lkp@intel.com/
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated AES-CBC-CTS</title>
<updated>2024-03-20T15:56:11+00:00</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2024-02-13T05:54:42+00:00</published>
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<id>urn:sha1:c70dfa4a2723ff5046fdc6d8a054713483f64f1b</id>
<content type='text'>
Add an implementation of cts(cbc(aes)) accelerated using the Zvkned
RISC-V vector crypto extension.  This is mainly useful for fscrypt,
where cts(cbc(aes)) is the "default" filenames encryption algorithm.  In
that use case, typically most messages are short and are block-aligned.
The CBC-CTS variant implemented is CS3; this is the variant Linux uses.

To perform well on short messages, the new implementation processes the
full message in one call to the assembly function if the data is
contiguous.  Otherwise it falls back to CBC operations followed by CTS
at the end.  For decryption, to further improve performance on short
messages, especially block-aligned messages, the CBC-CTS assembly
function parallelizes the AES decryption of all full blocks.  This
improves on the arm64 implementation of cts(cbc(aes)), which always
splits the CBC part(s) from the CTS part, doing the AES decryptions for
the last two blocks serially and usually loading the round keys twice.

Tested in QEMU with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y.

Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240213055442.35954-1-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - parallelize AES-CBC decryption</title>
<updated>2024-03-20T15:56:10+00:00</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2024-02-08T06:08:51+00:00</published>
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<id>urn:sha1:da215b089b5d4ff30745c59922b54b309d55a5d8</id>
<content type='text'>
Since CBC decryption is parallelizable, make the RISC-V implementation
of AES-CBC decryption process multiple blocks at a time, instead of
processing the blocks one by one.  This should improve performance.

Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240208060851.154129-1-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated SM4</title>
<updated>2024-01-23T01:55:24+00:00</updated>
<author>
<name>Jerry Shih</name>
<email>jerry.shih@sifive.com</email>
</author>
<published>2024-01-22T00:19:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b8d06352bbf397608a262c9d5f2b03ce32a3544a'/>
<id>urn:sha1:b8d06352bbf397608a262c9d5f2b03ce32a3544a</id>
<content type='text'>
Add an implementation of SM4 using the Zvksed extension.  The assembly
code is derived from OpenSSL code (openssl/openssl#21923) that was
dual-licensed so that it could be reused in the kernel.  Nevertheless,
the assembly has been significantly reworked for integration with the
kernel, for example by using a regular .S file instead of the so-called
perlasm, using the assembler instead of bare '.inst', and greatly
reducing code duplication.

Co-developed-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Signed-off-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Co-developed-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Jerry Shih &lt;jerry.shih@sifive.com&gt;
Co-developed-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240122002024.27477-11-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated SM3</title>
<updated>2024-01-23T01:55:23+00:00</updated>
<author>
<name>Jerry Shih</name>
<email>jerry.shih@sifive.com</email>
</author>
<published>2024-01-22T00:19:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=563a5255afa237c961c5c8c8c552425c519b88da'/>
<id>urn:sha1:563a5255afa237c961c5c8c8c552425c519b88da</id>
<content type='text'>
Add an implementation of SM3 using the Zvksh extension.  The assembly
code is derived from OpenSSL code (openssl/openssl#21923) that was
dual-licensed so that it could be reused in the kernel.  Nevertheless,
the assembly has been significantly reworked for integration with the
kernel, for example by using a regular .S file instead of the so-called
perlasm, using the assembler instead of bare '.inst', and greatly
reducing code duplication.

Co-developed-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Signed-off-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Co-developed-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Jerry Shih &lt;jerry.shih@sifive.com&gt;
Co-developed-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240122002024.27477-10-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated SHA-{512,384}</title>
<updated>2024-01-23T01:55:22+00:00</updated>
<author>
<name>Jerry Shih</name>
<email>jerry.shih@sifive.com</email>
</author>
<published>2024-01-22T00:19:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b3415925a08b13e468e8f3805bce86015475dd99'/>
<id>urn:sha1:b3415925a08b13e468e8f3805bce86015475dd99</id>
<content type='text'>
Add an implementation of SHA-512 and SHA-384 using the Zvknhb extension.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using a regular .S file
instead of the so-called perlasm, using the assembler instead of bare
'.inst', and greatly reducing code duplication.

Co-developed-by: Charalampos Mitrodimas &lt;charalampos.mitrodimas@vrull.eu&gt;
Signed-off-by: Charalampos Mitrodimas &lt;charalampos.mitrodimas@vrull.eu&gt;
Co-developed-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Co-developed-by: Phoebe Chen &lt;phoebe.chen@sifive.com&gt;
Signed-off-by: Phoebe Chen &lt;phoebe.chen@sifive.com&gt;
Signed-off-by: Jerry Shih &lt;jerry.shih@sifive.com&gt;
Co-developed-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240122002024.27477-9-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated SHA-{256,224}</title>
<updated>2024-01-23T01:55:21+00:00</updated>
<author>
<name>Jerry Shih</name>
<email>jerry.shih@sifive.com</email>
</author>
<published>2024-01-22T00:19:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8c8e40470ffeb7a279254c78c7779d7294a76ef1'/>
<id>urn:sha1:8c8e40470ffeb7a279254c78c7779d7294a76ef1</id>
<content type='text'>
Add an implementation of SHA-256 and SHA-224 using the Zvknha or Zvknhb
extension.  The assembly code is derived from OpenSSL code
(openssl/openssl#21923) that was dual-licensed so that it could be
reused in the kernel.  Nevertheless, the assembly has been significantly
reworked for integration with the kernel, for example by using a regular
.S file instead of the so-called perlasm, using the assembler instead of
bare '.inst', and greatly reducing code duplication.

Co-developed-by: Charalampos Mitrodimas &lt;charalampos.mitrodimas@vrull.eu&gt;
Signed-off-by: Charalampos Mitrodimas &lt;charalampos.mitrodimas@vrull.eu&gt;
Co-developed-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Co-developed-by: Phoebe Chen &lt;phoebe.chen@sifive.com&gt;
Signed-off-by: Phoebe Chen &lt;phoebe.chen@sifive.com&gt;
Signed-off-by: Jerry Shih &lt;jerry.shih@sifive.com&gt;
Co-developed-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240122002024.27477-8-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated GHASH</title>
<updated>2024-01-23T01:55:20+00:00</updated>
<author>
<name>Jerry Shih</name>
<email>jerry.shih@sifive.com</email>
</author>
<published>2024-01-22T00:19:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=600a3853dfa007935220b3489e2be5ab8950b4b4'/>
<id>urn:sha1:600a3853dfa007935220b3489e2be5ab8950b4b4</id>
<content type='text'>
Add an implementation of GHASH using the zvkg extension.  The assembly
code is derived from OpenSSL code (openssl/openssl#21923) that was
dual-licensed so that it could be reused in the kernel.  Nevertheless,
the assembly has been significantly reworked for integration with the
kernel, for example by using a regular .S file instead of the so-called
perlasm, using the assembler instead of bare '.inst', reducing code
duplication, and eliminating unnecessary endianness conversions.

Co-developed-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Signed-off-by: Christoph Müllner &lt;christoph.muellner@vrull.eu&gt;
Co-developed-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@vrull.eu&gt;
Signed-off-by: Jerry Shih &lt;jerry.shih@sifive.com&gt;
Co-developed-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240122002024.27477-7-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>crypto: riscv - add vector crypto accelerated ChaCha20</title>
<updated>2024-01-23T01:55:19+00:00</updated>
<author>
<name>Jerry Shih</name>
<email>jerry.shih@sifive.com</email>
</author>
<published>2024-01-22T00:19:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bb54668837a073f18e173dd7be63f9ef5ee9f7ac'/>
<id>urn:sha1:bb54668837a073f18e173dd7be63f9ef5ee9f7ac</id>
<content type='text'>
Add an implementation of ChaCha20 using the Zvkb extension.  The
assembly code is derived from OpenSSL code (openssl/openssl#21923) that
was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using a regular .S file
instead of the so-called perlasm, using the assembler instead of bare
'.inst', and reducing code duplication.

Signed-off-by: Jerry Shih &lt;jerry.shih@sifive.com&gt;
Co-developed-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240122002024.27477-6-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
</feed>
