kernel/linux.git/arch/riscv/boot, branch v6.6.131

riscv: dts: starfive: Fix a typo in StarFive JH7110 pin function definitions

2025-03-28T20:59:54+00:00

commit 1b133129ad6b28186214259af3bd5fc651a85509 upstream. Fix a typo in StarFive JH7110 pin function definitions for GPOUT_SYS_SDIO1_DATA4 Fixes: e22f09e598d12 ("riscv: dts: starfive: Add StarFive JH7110 pin function definitions") Signed-off-by: E Shattow Acked-by: Hal Feng CC: stable@vger.kernel.org Signed-off-by: Conor Dooley Signed-off-by: Greg Kroah-Hartman

riscv: dts: starfive: add assigned-clock* to limit frquency

2024-09-18T17:24:10+00:00

commit af571133f7ae028ec9b5fdab78f483af13bf28d3 upstream. In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley Signed-off-by: WangYuli Signed-off-by: Greg Kroah-Hartman

riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board

2024-06-16T11:47:45+00:00

commit 0f74c64f0a9f6e1e7cf17bea3d4350fa6581e0d7 upstream. Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. Originally the binding required one, so the dts patch added an invalid interrupt that the driver ignored (0) as the interrupt line of the PMIC is not actually connected on this platform. This went unnoticed during review as it would have been a valid interrupt for a GPIO controller, but it is not for the PLIC. The PLIC, on this platform at least, silently ignores the enablement of interrupt 0. Bo Gan is running a modified version of OpenSBI that faults if writes are done to reserved fields, so their kernel runs into problems. Delete the invalid interrupt from the device tree. Cc: stable@vger.kernel.org Reported-by: Bo Gan Link: https://lore.kernel.org/all/c8b6e960-2459-130f-e4e4-7c9c2ebaa6d3@gmail.com/ Signed-off-by: Shengyu Qu Fixes: 2378341504de ("riscv: dts: starfive: Enable axp15060 pmic for cpufreq") [conor: rewrite the commit message to add more detail] Signed-off-by: Conor Dooley Signed-off-by: Greg Kroah-Hartman

riscv: dts: starfive: visionfive 2: Remove non-existing TDM hardware

2024-06-12T09:12:20+00:00

[ Upstream commit dcde4e97b122ac318aaa71e8bcd2857dc28a0d12 ] This partially reverts commit e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") This added device tree nodes for TDM hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the I2S node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") Signed-off-by: Hannah Peuckmann Reviewed-by: Emil Renner Berthing Tested-by: Emil Renner Berthing Signed-off-by: Conor Dooley Signed-off-by: Sasha Levin

riscv: dts: sifive: add missing #interrupt-cells to pmic

2024-03-26T22:19:11+00:00

[ Upstream commit ce6b6d1513965f500a05f3facf223fa01fd74920 ] At W=2 dtc complains: hifive-unmatched-a00.dts:120.10-238.4: Warning (interrupt_provider): /soc/i2c@10030000/pmic@58: Missing '#interrupt-cells' in interrupt provider Add the missing property. Reviewed-by: Samuel Holland Signed-off-by: Conor Dooley Signed-off-by: Sasha Levin

riscv: boot: Fix creation of loader.bin

2023-11-20T10:59:35+00:00

[ Upstream commit 57a4542cb7c9baa1509c3366b57a08d75b212ead ] When flashing loader.bin for K210 using kflash: [ERROR] This is an ELF file and cannot be programmed to flash directly: arch/riscv/boot/loader.bin Before, loader.bin relied on "OBJCOPYFLAGS := -O binary" in the main RISC-V Makefile to create a boot image with the right format. With this removed, the image is now created in the wrong (ELF) format. Fix this by adding an explicit rule. Fixes: 505b02957e74f0c5 ("riscv: Remove duplicate objcopy flag") Signed-off-by: Geert Uytterhoeven Reviewed-by: Damien Le Moal Link: https://lore.kernel.org/r/1086025809583809538dfecaa899892218f44e7e.1698159066.git.geert+renesas@glider.be Signed-off-by: Palmer Dabbelt Signed-off-by: Sasha Levin

riscv: dts: allwinner: remove address-cells from intc node

2023-11-20T10:59:14+00:00

[ Upstream commit 267860b10c67dd396c73a9e6e8103670d78a4c01 ] A recent submission [1] from Rob has added additionalProperties: false to the interrupt-controller child node of RISC-V cpus, highlighting that the D1 DT has been incorrectly using #address-cells since its introduction. It has no child nodes, so #address-cells is not needed. Remove it. Fixes: 077e5f4f5528 ("riscv: dts: allwinner: Add the D1/D1s SoC devicetree") Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1] Signed-off-by: Conor Dooley Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230916-saddling-dastardly-8cf6d1263c24@spud Signed-off-by: Jernej Skrabec Signed-off-by: Sasha Levin

riscv: dts: thead: set dma-noncoherent to soc bus

2023-10-17T19:00:24+00:00

riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't dma coherent, so set dma-noncoherent to reflect this fact. Signed-off-by: Jisheng Zhang Tested-by: Drew Fustini Reviewed-by: Guo Ren Signed-off-by: Arnd Bergmann

riscv: dts: starfive: visionfive 2: correct spi's ss pin

2023-10-12T09:23:23+00:00

The ss pin of spi0 is the same as sck pin. According to the visionfive 2 documentation, it should be pin 49 instead of 48. Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") Reviewed-by: Emil Renner Berthing Signed-off-by: Nam Cao Signed-off-by: Conor Dooley

riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order

2023-09-13T13:24:56+00:00

Node uart0_pins should be sorted alphabetically. Signed-off-by: Hal Feng Signed-off-by: Conor Dooley