kernel/linux.git/arch/riscv/boot, branch v6.18.22

riscv: boot: Always make Image from vmlinux, not vmlinux.unstripped

2026-01-17T15:35:12+00:00

commit 66562b66dcbc8f93c1e28632299f449bb2f5c47d upstream. Since commit 4b47a3aefb29 ("kbuild: Restore pattern to avoid stripping .rela.dyn from vmlinux") vmlinux has .rel*.dyn preserved. Therefore, use vmlinux to produce Image, not vmlinux.unstripped. Doing so fixes booting a RELOCATABLE=y Image with kexec. The problem is caused by this chain of events: - Since commit 3e86e4d74c04 ("kbuild: keep .modinfo section in vmlinux.unstripped"), vmlinux.unstripped gets a .modinfo section. - The .modinfo section has SHF_ALLOC, so it ends up in Image, at the end of it. - The Image header's image_size field does not expect to include .modinfo and does not account for it, since it should not be in Image. - If .modinfo is large enough, the file size of Image ends up larger than image_size, which eventually leads to it failing sanity_check_segment_list(). Using vmlinux instead of vmlinux.unstripped means that the unexpected .modinfo section is gone from Image, fixing the file size problem. Cc: stable@vger.kernel.org Fixes: 3e86e4d74c04 ("kbuild: keep .modinfo section in vmlinux.unstripped") Signed-off-by: Vivian Wang Reviewed-by: Nathan Chancellor Tested-by: Han Gao Link: https://patch.msgid.link/20251230-riscv-vmlinux-not-unstripped-v1-1-15f49df880df@iscas.ac.cn Signed-off-by: Paul Walmsley Signed-off-by: Greg Kroah-Hartman

riscv: dts: allwinner: d1: fix vlenb property

2025-11-22T01:19:42+00:00

According to [1], the C906 vector registers are 128 bits wide. The 'thead,vlenb' property specifies the vector register length in bytes, so its value must be set to 16. [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") Signed-off-by: Sergey Matyukevich Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com Signed-off-by: Chen-Yu Tsai

Merge tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next

2025-10-02T22:17:01+00:00

Pull networking updates from Paolo Abeni: "Core & protocols: - Improve drop account scalability on NUMA hosts for RAW and UDP sockets and the backlog, almost doubling the Pps capacity under DoS - Optimize the UDP RX performance under stress, reducing contention, revisiting the binary layout of the involved data structs and implementing NUMA-aware locking. This improves UDP RX performance by an additional 50%, even more under extreme conditions - Add support for PSP encryption of TCP connections; this mechanism has some similarities with IPsec and TLS, but offers superior HW offloads capabilities - Ongoing work to support Accurate ECN for TCP. AccECN allows more than one congestion notification signal per RTT and is a building block for Low Latency, Low Loss, and Scalable Throughput (L4S) - Reorganize the TCP socket binary layout for data locality, reducing the number of touched cachelines in the fastpath - Refactor skb deferral free to better scale on large multi-NUMA hosts, this improves TCP and UDP RX performances significantly on such HW - Increase the default socket memory buffer limits from 256K to 4M to better fit modern link speeds - Improve handling of setups with a large number of nexthop, making dump operating scaling linearly and avoiding unneeded synchronize_rcu() on delete - Improve bridge handling of VLAN FDB, storing a single entry per bridge instead of one entry per port; this makes the dump order of magnitude faster on large switches - Restore IP ID correctly for encapsulated packets at GSO segmentation time, allowing GRO to merge packets in more scenarios - Improve netfilter matching performance on large sets - Improve MPTCP receive path performance by leveraging recently introduced core infrastructure (skb deferral free) and adopting recent TCP autotuning changes - Allow bridges to redirect to a backup port when the bridge port is administratively down - Introduce MPTCP 'laminar' endpoint that con be used only once per connection and simplify common MPTCP setups - Add RCU safety to dst->dev, closing a lot of possible races - A significant crypto library API for SCTP, MPTCP and IPv6 SR, reducing code duplication - Supports pulling data from an skb frag into the linear area of an XDP buffer Things we sprinkled into general kernel code: - Generate netlink documentation from YAML using an integrated YAML parser Driver API: - Support using IPv6 Flow Label in Rx hash computation and RSS queue selection - Introduce API for fetching the DMA device for a given queue, allowing TCP zerocopy RX on more H/W setups - Make XDP helpers compatible with unreadable memory, allowing more easily building DevMem-enabled drivers with a unified XDP/skbs datapath - Add a new dedicated ethtool callback enabling drivers to provide the number of RX rings directly, improving efficiency and clarity in RX ring queries and RSS configuration - Introduce a burst period for the health reporter, allowing better handling of multiple errors due to the same root cause - Support for DPLL phase offset exponential moving average, controlling the average smoothing factor Device drivers: - Add a new Huawei driver for 3rd gen NIC (hinic3) - Add a new SpacemiT driver for K1 ethernet MAC - Add a generic abstraction for shared memory communication devices (dibps) - Ethernet high-speed NICs: - nVidia/Mellanox: - Use multiple per-queue doorbell, to avoid MMIO contention issues - support adjacent functions, allowing them to delegate their SR-IOV VFs to sibling PFs - support RSS for IPSec offload - support exposing raw cycle counters in PTP and mlx5 - support for disabling host PFs. - Intel (100G, ice, idpf): - ice: support for SRIOV VFs over an Active-Active link aggregate - ice: support for firmware logging via debugfs - ice: support for Earliest TxTime First (ETF) hardware offload - idpf: support basic XDP functionalities and XSk - Broadcom (bnxt): - support Hyper-V VF ID - dynamic SRIOV resource allocations for RoCE - Meta (fbnic): - support queue API, zero-copy Rx and Tx - support basic XDP functionalities - devlink health support for FW crashes and OTP mem corruptions - expand hardware stats coverage to FEC, PHY, and Pause - Wangxun: - support ethtool coalesce options - support for multiple RSS contexts - Ethernet virtual: - Macsec: - replace custom netlink attribute checks with policy-level checks - Bonding: - support aggregator selection based on port priority - Microsoft vNIC: - use page pool fragments for RX buffers instead of full pages to improve memory efficiency - Ethernet NICs consumer, and embedded: - Qualcomm: support Ethernet function for IPQ9574 SoC - Airoha: implement wlan offloading via NPU - Freescale - enetc: add NETC timer PTP driver and add PTP support - fec: enable the Jumbo frame support for i.MX8QM - Renesas (R-Car S4): - support HW offloading for layer 2 switching - support for RZ/{T2H, N2H} SoCs - Cadence (macb): support TAPRIO traffic scheduling - TI: - support for Gigabit ICSS ethernet SoC (icssm-prueth) - Synopsys (stmmac): a lot of cleanups - Ethernet PHYs: - Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS driver - Support bcm63268 GPHY power control - Support for Micrel lan8842 PHY and PTP - Support for Aquantia AQR412 and AQR115 - CAN: - a large CAN-XL preparation work - reorganize raw_sock and uniqframe struct to minimize memory usage - rcar_canfd: update the CAN-FD handling - WiFi: - extended Neighbor Awareness Networking (NAN) support - S1G channel representation cleanup - improve S1G support - WiFi drivers: - Intel (iwlwifi): - major refactor and cleanup - Broadcom (brcm80211): - support for AP isolation - RealTek (rtw88/89) rtw88/89: - preparation work for RTL8922DE support - MediaTek (mt76): - HW restart improvements - MLO support - Qualcomm/Atheros (ath10k): - GTK rekey fixes - Bluetooth drivers: - btusb: support for several new IDs for MT7925 - btintel: support for BlazarIW core - btintel_pcie: support for _suspend() / _resume() - btintel_pcie: support for Scorpious, Panther Lake-H484 IDs" * tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1536 commits) net: stmmac: Add support for Allwinner A523 GMAC200 dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Revert "Documentation: net: add flow control guide and document ethtool API" octeontx2-pf: fix bitmap leak octeontx2-vf: fix bitmap leak net/mlx5e: Use extack in set rxfh callback net/mlx5e: Introduce mlx5e_rss_params for RSS configuration net/mlx5e: Introduce mlx5e_rss_init_params net/mlx5e: Remove unused mdev param from RSS indir init net/mlx5: Improve QoS error messages with actual depth values net/mlx5e: Prevent entering switchdev mode with inconsistent netns net/mlx5: HWS, Generalize complex matchers net/mlx5: Improve write-combining test reliability for ARM64 Grace CPUs selftests/net: add tcp_port_share to .gitignore Revert "net/mlx5e: Update and set Xon/Xoff upon MTU set" net: add NUMA awareness to skb_attempt_defer_free() net: use llist for sd->defer_list net: make softnet_data.defer_count an atomic selftests: drv-net: psp: add tests for destroying devices selftests: drv-net: psp: add test for auto-adjusting TCP MSS ...

Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-10-02T00:19:38+00:00

Pull SoC dt updates from Arnd Bergmann: "There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation" * tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits) arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node ARM: dts: microchip: sam9x7: Add qspi controller arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes arm64: dts: allwinner: h313: Add Amediatech X96Q dt-bindings: arm: sunxi: Add Amediatech X96Q arm64: dts: apple: t8015: Add SPMI node arm64: dts: apple: t8012: Add SPMI node arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT arm64: dts: rockchip: update pinctrl names for Radxa E52C arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C arm64: dts: apple: Add J474s, J475c and J475d device trees arm64: dts: apple: Add J414 and J416 Macbook Pro device trees arm64: dts: apple: Add initial t6020/t6021/t6022 DTs ...

Merge tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-10-02T00:10:27+00:00

Pull new SoC support from Arnd Bergmann: "Pinkesh Vaghela adds support for the ESWIN EIC7700 SoC consisting of SiFive Quad-Core P550 CPU cluster and the first development board that uses it, the SiFive HiFive Premier P550 [1]. This adds initial device tree and also adds ESWIN architecture support. Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier P550 board using U-Boot 2024.01 and OpenSBI 1.4" Link: https://lore.kernel.org/linux-riscv/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/ [1] * tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: riscv: dts: eswin: add HiFive Premier P550 board device tree riscv: dts: add initial support for EIC7700 SoC dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC dt-bindings: riscv: Add SiFive HiFive Premier P550 board riscv: Add Kconfig option for ESWIN platforms dt-bindings: riscv: Add SiFive P550 CPU compatible

Merge tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2025-09-30T23:00:29+00:00

Pull irq chip driver updates from Thomas Gleixner: - Use the startup/shutdown callbacks for the PCI/MSI per device interrupt domains. This allows us to initialize the RISCV PLIC interrupt hierarchy correctly and provides a mechanism to decouple the masking and unmasking during run-time from the expensive PCI mask and unmask when the underlying MSI provider implementation allows the interrupt to be masked. - Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that the affinity assignment works correctly by switching it over to the startup/shutdown scheme - Allow MSI providers to opt out from masking a PCI/MSI interrupt at the PCI device during operation when the provider can mask the interrupt at the underlying interrupt chip. This reduces the overhead in scenarios where disable_irq()/enable_irq() is utilized frequently by a driver. The PCI/MSI device level [un]masking is only required on startup and shutdown in this case. - Remove the conditional mask/unmask logic in the PCI/MSI layer as this is now handled unconditionally. - Replace the hardcoded interrupt routing in the Loongson EIOINTC interrupt driver to respect the firmware settings and spread them out to different CPU interrupt inputs so that the demultiplexing handler only needs to read only a single 64-bit status register instead of four, which significantly reduces the overhead in VMs as the status register access causes a VM exit. - Add support for the new AST2700 SCU interrupt controllers - Use the legacy interrupt domain setup for the Loongson PCH-LPC interrupt controller, which resembles the x86 legacy PIC setup and has the same hardcoded legacy requirements. - The usual set of cleanups, fixes and improvements all over the place * tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controller PCI/MSI: Remove the conditional parent [un]mask logic irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flag irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc() irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup path irqchip/gic-v5: Delete a stray tab irqchip/sg2042-msi: Set irq type according to DT configuration riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING irqchip/gic-v2m: Handle Multiple MSI base IRQ Alignment irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM irqchip: Use int type to store negative error codes irqchip/gic-v5: Remove the redundant ITS cache invalidation PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent() irqchip/loongson-eiointc: Add multiple interrupt pin routing support irqchip/loongson-eiointc: Route interrupt parsed from bios table ...

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2025-09-25T18:00:59+00:00

Cross-merge networking fixes after downstream PR (net-6.17-rc8). Conflicts: drivers/net/can/spi/hi311x.c 6b6968084721 ("can: hi311x: fix null pointer dereference when resuming from sleep before interface was enabled") 27ce71e1ce81 ("net: WQ_PERCPU added to alloc_workqueue users") https://lore.kernel.org/72ce7599-1b5b-464a-a5de-228ff9724701@kernel.org net/smc/smc_loopback.c drivers/dibs/dibs_loopback.c a35c04de2565 ("net/smc: fix warning in smc_rx_splice() when calling get_page()") cc21191b584c ("dibs: Move data path to dibs layer") https://lore.kernel.org/74368a5c-48ac-4f8e-a198-40ec1ed3cf5f@kernel.org Adjacent changes: drivers/net/dsa/lantiq/lantiq_gswip.c c0054b25e2f1 ("net: dsa: lantiq_gswip: move gswip_add_single_port_br() call to port_setup()") 7a1eaef0a791 ("net: dsa: lantiq_gswip: support model-specific mac_select_pcs()") Signed-off-by: Jakub Kicinski

riscv: dts: eswin: add HiFive Premier P550 board device tree

2025-09-25T06:29:06+00:00

Add minimal device tree for HiFive Premier P550 Development board Currently the data populated in this DT file is for UART. Signed-off-by: Min Lin Co-developed-by: Pinkesh Vaghela Signed-off-by: Pinkesh Vaghela Tested-by: Samuel Holland Tested-by: Ariel D'Alessandro Reviewed-by: Samuel Holland Link: https://lore.kernel.org/r/20250825132427.1618089-7-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann

riscv: dts: add initial support for EIC7700 SoC

2025-09-25T06:29:06+00:00

Add initial support for EIC7700 SoC that uses a SiFive Quad-Core P550 CPU cluster. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Min Lin Co-developed-by: Pritesh Patel Signed-off-by: Pritesh Patel Co-developed-by: Darshan Prajapati Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Link: https://lore.kernel.org/r/20250825132427.1618089-6-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann

Merge tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

2025-09-24T21:24:46+00:00

RISC-V Misc Devicetrees for v6.18 Starfive: The main new addition is support for the JH7110 Milk-V Mars CM lite SoM. Other than that, there's several cleanups done to the common JH7110 dtsi file, some relating to properties used by U-Boot or encountered during U-Boot development. Additionally, there's a binding and devicetree node for the memory controller on the JH7110. The memory controller only sees use in U-Boot, so the binding is here rather than in Krzysztof's branch. SiFive: Support for SiFive vendor-specific extensions in the binding file for extensions. These currently only see use in the SBI implementation. Microchip: Addition of support for the PolarFire SoC Discovery kit and non-engineering sample Icicle kit. The latter differs very slightly from the final ES devices due to bug fixes affecting functionality, and needs its own dts. To reduce duplication, the common portion of the two Icicle kits are moved into a dtsi. There's a few minor fixes here too, mostly low-hanging fruit detected during the addition of the Discovery kit that were then applied to the Icicle. Signed-off-by: Conor Dooley * tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module dt-bindings: riscv: starfive: add milkv,marscm-lite riscv: dts: starfive: add Milk-V Mars CM system-on-module dt-bindings: riscv: starfive: add milkv,marscm-emmc riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants riscv: dts: microchip: add a device tree for Discovery Kit dt-bindings: riscv: microchip: document Discovery Kit riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes riscv: dts: microchip: add icicle kit with production device dt-bindings: riscv: microchip: document icicle kit with production device riscv: dts: microchip: add common board dtsi for icicle kit variants riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1 riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader riscv: dts: starfive: jh7110: add DMC memory controller dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1 riscv: dts: microchip: Minor whitespace cleanup dt-bindings: riscv: Add SiFive vendor extensions description Link: https://lore.kernel.org/r/20250924-frighten-magazine-ee2f16e64638@spud Signed-off-by: Arnd Bergmann