kernel/linux.git/arch/powerpc/lib/sstep.c, branch linux-4.7.y

powerpc/sstep: Fix emulation fall-through

2016-05-11T11:54:08+00:00

There is a switch fallthough in instr_analyze() which can cause an invalid instruction to be emulated as a different, valid, instruction. The rld* (opcode 30) case extracts a sub-opcode from bits 3:1 of the instruction word. However, the only valid values of this field are 001 and 000. These cases are correctly handled, but the others are not which causes execution to fall through into case 31. Breaking out of the switch causes the instruction to be marked as unknown and allows the caller to deal with the invalid instruction in a manner consistent with other invalid instructions. Signed-off-by: Oliver O'Halloran Signed-off-by: Michael Ellerman

powerpc/sstep: Fix sstep.c compile on powerpcspe

2016-05-11T11:54:07+00:00

Commit be96f63375a1 ("powerpc: Split out instruction analysis part of emulate_step()") introduced ldarx and stdcx into the instructions in sstep.c, which are not accepted by the assembler on powerpcspe, but does seem to be accepted by the normal powerpc assembler even in 32 bit mode. Wrap these two instructions in a __powerpc64__ check like it is everywhere else in the file. Fixes: be96f63375a1 ("powerpc: Split out instruction analysis part of emulate_step()") Signed-off-by: Len Sorensen Signed-off-by: Michael Ellerman

powerpc: Fix compilation of emulate_step()

2014-11-12T04:54:29+00:00

Commit be96f63375a1 ("powerpc: Split out instruction analysis part of emulate_step()") added some calls to do_fp_load() and do_fp_store(), which fail to compile on configs with CONFIG_PPC_FPU=n and CONFIG_PPC_EMULATE_SSTEP=y. This fixes the compile by adding #ifdef CONFIG_PPC_FPU around the code that calls these functions. Signed-off-by: Paul Mackerras Signed-off-by: Michael Ellerman

powerpc: Implement emulation of string loads and stores

2014-09-25T13:14:52+00:00

The size field of the op.type word is now the total number of bytes to be loaded or stored. Signed-off-by: Paul Mackerras Signed-off-by: Michael Ellerman

powerpc: Emulate icbi, mcrf and conditional-trap instructions

2014-09-25T13:14:51+00:00

This extends the instruction emulation done by analyse_instr() and emulate_step() to handle a few more instructions that are found in the kernel. Signed-off-by: Paul Mackerras Signed-off-by: Michael Ellerman

powerpc: Split out instruction analysis part of emulate_step()

2014-09-25T13:14:51+00:00

This splits out the instruction analysis part of emulate_step() into a separate analyse_instr() function, which decodes the instruction, but doesn't execute any load or store instructions. It does execute integer instructions and branches which can be executed purely by updating register values in the pt_regs struct. For other instructions, it returns the instruction type and other details in a new instruction_op struct. emulate_step() then uses that information to execute loads, stores, cache operations, mfmsr, mtmsr[d], and (on 64-bit) sc instructions. The reason for doing this is so that the KVM code can use it instead of having its own separate instruction emulation code. Possibly the alignment interrupt handler could also use this. Signed-off-by: Paul Mackerras Signed-off-by: Michael Ellerman

powerpc: Fix bugs in emulate_step()

2014-07-22T05:55:51+00:00

This fixes some bugs in emulate_step(). First, the setting of the carry bit for the arithmetic right-shift instructions was not correct on 64-bit machines because we were masking with a mask of type int rather than unsigned long. Secondly, the sld (shift left doubleword) instruction was using the wrong instruction field for the register containing the shift count. Signed-off-by: Paul Mackerras Signed-off-by: Benjamin Herrenschmidt

powerpc: fix typo 'CONFIG_PPC_CPU'

2014-06-11T07:04:25+00:00

Commit cd64d1697cf0 ("powerpc: mtmsrd not defined") added a check for CONFIG_PPC_CPU were a check for CONFIG_PPC_FPU was clearly intended. Fixes: cd64d1697cf0 ("powerpc: mtmsrd not defined") Signed-off-by: Paul Bolle Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix Unaligned LE Floating Point Loads and Stores

2013-10-30T05:01:36+00:00

This patch addresses unaligned single precision floating point loads and stores in the single-step code. The old implementation improperly treated an 8 byte structure as an array of two 4 byte words, which is a classic little endian bug. Signed-off-by: Tom Musta Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix Unaligned Loads and Stores

2013-10-30T05:01:30+00:00

This patch modifies the unaligned access routines of the sstep.c module so that it properly reverses the bytes of storage operands in the little endian kernel kernel. This is implemented by breaking an unaligned little endian access into a combination of single byte accesses plus an overal byte reversal operation. Signed-off-by: Tom Musta Signed-off-by: Benjamin Herrenschmidt