kernel/linux.git/arch/mips/oprofile, branch v4.9.331

MIPS/Loongson-3: Convert oprofile to hotplug state machine

2016-07-15T08:40:29+00:00

Install the callbacks via the state machine and let the core invoke the callbacks on the already online CPUs. Signed-off-by: Richard Cochran Signed-off-by: Anna-Maria Gleixner Reviewed-by: Sebastian Andrzej Siewior Acked-by: Ralf Baechle Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Robert Richter Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Cc: rt@linutronix.de Link: http://lkml.kernel.org/r/20160713153337.054827168@linutronix.de Signed-off-by: Ingo Molnar

MIPS: oprofile: Fix typo

2016-05-28T10:35:09+00:00

Signed-off-by: Andrea Gelmini Cc: rric@kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/13334/ Signed-off-by: Ralf Baechle

MIPS: Add perf counter feature

2016-05-13T13:30:25+00:00

Add CPU feature for standard MIPS r2 performance counters, as determined by the Config1.PC bit. Both perf_events and oprofile probe this bit, so lets combine the probing and change both to use cpu_has_perf. This will also be used for VZ support in KVM to know whether performance counters exist which can be exposed to guests. [ralf@linux-mips.org: resolve conflict.] Signed-off-by: James Hogan Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Robert Richter Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/13226/ Signed-off-by: Ralf Baechle

MIPS: oprofile: Fix a preemption issue

2016-05-09T10:00:03+00:00

Use boot_cpu_type() instead of current_cpu_type() in oprofile_arch_init() to avoid the below warning, cpu_type is normally consistent in a MIPS SMP system. There are a few exceptions such as SGI servers where it is possible to mix R10000, R12000, R14000 and R16000 within certain constraints. Let's not worry about those now. BUG: using smp_processor_id() in preemptible [00000000] code: insmod/952 caller is oprofile_arch_init+0x30/0x194 [oprofile] CPU: 5 PID: 952 Comm: insmod Not tainted 4.1.13-WR8.0.0.0_standard #1 Stack : ffffffff80c10000 0000000000000001 8000000025bf0790 ffffffff80e10000 ffffffff80e50000 ffffffff80254e2c ffffffff80b64428 ffffffff80e10790 0000000000000000 ffffffff801caeb8 0000000000000045 0000000000000005 ffffffff80c10000 ffffffff801cb798 0000000000000000 ffffffff80e30000 0000000000000000 ffffffff801ff1c0 ffffffff80e2d2f8 000000000000000b ffffffff801cbba0 ffffffff80e107b0 ffffffff80a77828 0000000000000005 00000000000003b8 ffffffff80e2d2f8 800000040ad39960 ffffffff801f9950 0000000000000124 80000004093b7990 80000004093b7ab8 ffffffff80925108 ffffffff80b69a07 ffffffff80a6f0d0 8000000407240e00 ffffffff801cc934 000000000000005d ffffffff80159080 0000000000000005 00000000000003b8 ... Call Trace: [] show_stack+0xe8/0x108 [] dump_stack+0x8c/0xd8 [] check_preemption_disabled+0x110/0x118 [] oprofile_arch_init+0x30/0x194 [oprofile] [] oprofile_init+0x2c/0xc0 [oprofile] [] do_one_initcall+0xa0/0x1c0 [] do_init_module+0x80/0x1d8 [] load_module+0x1b74/0x2278 [] SyS_finit_module+0xcc/0xf0 [] handle_sysn32+0x44/0x70 [ralf@linux-mips.org: Correct commit message.] Signed-off-by: Yanjiang Jin Cc: rric@kernel.org Cc: jinyanjiang@gmail.com Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11769/ Signed-off-by: Ralf Baechle

MIPS: Add cases for CPU_I6400

2015-08-26T13:23:03+00:00

Add a CPU_I6400 case to various switch statements, doing the same thing as for CPU_P5600. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10635/ Signed-off-by: Ralf Baechle

MIPS: Add R16000 detection

2015-04-01T15:22:13+00:00

This allows the kernel to correctly detect an R16000 MIPS CPU on systems that have those. Otherwise, such systems will detect the CPU as an R14000, due to similarities in the CPU PRId value. Signed-off-by: Joshua Kinard Cc: Linux MIPS List Patchwork: https://patchwork.linux-mips.org/patch/9092/ Signed-off-by: Ralf Baechle

MIPS: OProfile: Allow sharing IRQ with timer

2015-03-31T10:04:12+00:00

When requesting the performance counter overflow interrupt, pass flags which are compatible with the cevt-r4k driver, in particular IRQF_SHARED so that the two handlers can share the same IRQ. This is possible since release 2 of the architecture where there are separate pending interrupt bits for the timer interrupt and the performance counter interrupt. This will be necessary since the FDC interrupt can also be arbitrarily routed to a CPU interrupt, possibly sharing with the timer, the performance counters, or both, and it isn't scalable to have all the handlers able to call other handlers that may be on the same IRQ line. Signed-off-by: James Hogan Cc: Robert Richter Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9130/ Signed-off-by: Ralf Baechle

MIPS: Remove redundant IPTI==IPPCI logic

2015-03-31T10:04:12+00:00

The situation where the timer interrupt is on the same line as the performance counter interrupt is handled in per_cpu_trap_init() by setting cp0_perfcount_irq to -1, so there is no need to duplicate the logic conditional upon cp0_perfcount_irq >= 0 in perf (init_hw_perf_events()) and oprofile (mipsxx_init()). Signed-off-by: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9125/ Signed-off-by: Ralf Baechle

MIPS: cevt-r4k: Use CAUSEF_TI, CAUSEF_PCI constants

2015-03-31T10:04:12+00:00

Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than the magic values (1 << 30) and (1 << 26). Signed-off-by: James Hogan Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9124/ Signed-off-by: Ralf Baechle

MIPS: oprofile: Backtrace: don't fail on leaf functions

2014-11-24T06:45:31+00:00

Continue the backtrace if we cannot find SP adjustment and RA save. In that case, just assume the current RA. This allows us to get samples of frequent callers of e.g. GLIBC memset(). Signed-off-by: Aaro Koskinen Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8109/ Signed-off-by: Ralf Baechle