<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/arch/mips/include/asm/uasm.h, branch linux-4.16.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.16.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.16.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2017-06-28T10:22:39+00:00</updated>
<entry>
<title>MIPS: Add some instructions to uasm.</title>
<updated>2017-06-28T10:22:39+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2017-06-13T22:28:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dc190129f1c16e025a42a9c3717de7ed47fc6e2f'/>
<id>urn:sha1:dc190129f1c16e025a42a9c3717de7ed47fc6e2f</id>
<content type='text'>
Follow on patches for eBPF JIT require these additional instructions:

   insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu,
   insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav,
   insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor,
   insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu

... so, add them.

Sort the insn_* enumeration values alphabetically.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: Alexei Starovoitov &lt;ast@kernel.org&gt;
Cc: Daniel Borkmann &lt;daniel@iogearbox.net&gt;
Cc: Matt Redfearn &lt;matt.redfearn@imgtec.com&gt;
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16367/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Remove needless ISA abstraction</title>
<updated>2017-04-12T11:52:21+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2017-03-30T21:52:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=33679a50370db9aa1a3f0cdf5f70c1c07236a4b2'/>
<id>urn:sha1:33679a50370db9aa1a3f0cdf5f70c1c07236a4b2</id>
<content type='text'>
We always either target MIPS32/MIPS64 or microMIPS, and always include
one &amp; only one of uasm-mips.c or uasm-micromips.c. Therefore the
abstraction of the ISA in asm/uasm.h declaring functions for either ISA
is redundant &amp; needless. Remove it to simplify the code.

This is largely the result of the following:

  :%s/ISAOPC(\(.\{-}\))/uasm_i##\1/
  :%s/ISAFUNC(\(.\{-}\))/\1/

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/15844/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add support for LHU.</title>
<updated>2017-04-10T09:56:04+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2017-03-14T21:21:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bfbfa9d61cf29f3579107892c7347c02d891dfec'/>
<id>urn:sha1:bfbfa9d61cf29f3579107892c7347c02d891dfec</id>
<content type='text'>
The follow-on BPF JIT patches use the LHU instruction, so add it.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: Alexei Starovoitov &lt;ast@kernel.org&gt;
Cc: Steven J. Hill &lt;steven.hill@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15743/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add include guards in asm/uasm.h</title>
<updated>2017-02-03T15:19:01+00:00</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-09-10T22:53:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=93a93c2461f9416a58c7d1e32fec201af8cc3aad'/>
<id>urn:sha1:93a93c2461f9416a58c7d1e32fec201af8cc3aad</id>
<content type='text'>
Add include guards in asm/uasm.h to allow it to be safely used by a new
header asm/tlbex.h in the next patch to expose TLB exception building
functions for KVM to use.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: "Radim Krčmář" &lt;rkrcmar@redhat.com&gt;
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
</content>
</entry>
<entry>
<title>MIPS: uasm: Add MTHI/MTLO instructions</title>
<updated>2016-07-05T14:08:35+00:00</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-06-23T16:34:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9f730a60e5a046230cff8c9f4c8eb73f6dca7d81'/>
<id>urn:sha1:9f730a60e5a046230cff8c9f4c8eb73f6dca7d81</id>
<content type='text'>
Add MTHI/MTLO instructions for writing to the hi &amp; lo registers to uasm
so that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add DI instruction</title>
<updated>2016-07-05T14:08:29+00:00</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-06-23T16:34:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=61c64cf99ae589af3835dbc9bb57200d4a4842ae'/>
<id>urn:sha1:61c64cf99ae589af3835dbc9bb57200d4a4842ae</id>
<content type='text'>
Add DI instruction for disabling interrupts to uasm so that KVM can use
uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add CFCMSA/CTCMSA instructions</title>
<updated>2016-07-05T14:08:20+00:00</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-06-23T16:34:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=59e3559f48dcad3051f60c32775e028cd999ae53'/>
<id>urn:sha1:59e3559f48dcad3051f60c32775e028cd999ae53</id>
<content type='text'>
Add CFCMSA/CTCMSA instructions for accessing MSA control registers to
uasm so that KVM can use uasm for generating its entry point code at
runtime.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>MIPS: uasm: Add CFC1/CTC1 instructions</title>
<updated>2016-07-05T14:08:11+00:00</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2016-06-23T16:34:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c29732a179c2ed0cb9f001a8dc07dcf432389313'/>
<id>urn:sha1:c29732a179c2ed0cb9f001a8dc07dcf432389313</id>
<content type='text'>
Add CFC1/CTC1 instructions for accessing FP control registers to uasm so
that KVM can use uasm for generating its entry point code at runtime.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson-3: Fast TLB refill handler</title>
<updated>2016-05-13T12:02:15+00:00</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2016-03-03T01:45:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=380cd582c08831217ae693c86411902e6300ba6b'/>
<id>urn:sha1:380cd582c08831217ae693c86411902e6300ba6b</id>
<content type='text'>
Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.

[ralf@linux-mips.org: Resolve conflict.]

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Cc: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Cc: Steven J . Hill &lt;sjhill@realitydiluted.com&gt;
Cc: Fuxin Zhang &lt;zhangfx@lemote.com&gt;
Cc: Zhangjin Wu &lt;wuzhangjin@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12754/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add MFHC0 and MTHC0 instructions to uasm.</title>
<updated>2014-11-24T21:47:31+00:00</updated>
<author>
<name>Steven J. Hill</name>
<email>Steven.Hill@imgtec.com</email>
</author>
<published>2014-11-13T15:52:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e2965cd0003f222bd49f67907c2bc6ed691c6d20'/>
<id>urn:sha1:e2965cd0003f222bd49f67907c2bc6ed691c6d20</id>
<content type='text'>
New instructions for Extended Physical Addressing (XPA) functionality.

Signed-off-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8453/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
