kernel/linux.git/arch/mips/include/asm/time.h, branch v6.6.134

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

MIPS: Convert update_persistent_clock() to update_persistent_clock64()

2018-05-14T22:58:23+00:00

Since struct timespec is not y2038 safe on 32bit machines, this patch converts update_persistent_clock() to update_persistent_clock64() using struct timespec64. The rtc_mips_set_time() and rtc_mips_set_mmss() interfaces were using 'unsigned long' type that is not y2038 safe on 32bit machines, moreover there is only one platform implementing rtc_mips_set_time() and two platforms implementing rtc_mips_set_mmss(), so we can just make them each implement update_persistent_clock64() directly, to get that helper out of the common mips code by removing rtc_mips_set_time() and rtc_mips_set_mmss() interfaces. Signed-off-by: Baolin Wang Acked-by: Arnd Bergmann Cc: Ralf Baechle Cc: Huacai Chen Cc: Paul Burton Cc: linux-mips@linux-mips.org Signed-off-by: James Hogan

MIPS: Remove "weak" from get_c0_compare_int() declaration

2015-09-03T10:07:38+00:00

Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d711ed7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). get_c0_compare_int() is defined in several files. Each definition is weak, so I assume Kconfig prevents two or more from being included. The caller contains default code used when get_c0_compare_int() isn't defined at all. Add a weak get_c0_compare_int() definition with the default code and remove the weak annotation from the declaration. Then the platform implementations will be strong and will override the weak default. If multiple platforms are ever configured in, we'll get a link error instead of calling a random platform's implementation. Signed-off-by: Bjorn Helgaas Reviewed-by: James Hogan Cc: Andrew Bresticker Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10686/ Signed-off-by: Ralf Baechle

clocksource: mips-gic: Use CPU notifiers to setup the timer

2014-11-24T06:45:16+00:00

Instead of requiring an explicit call to gic_clockevent_init in the SMP startup path, use CPU notifiers to register and enable the GIC timer on CPU startup. Signed-off-by: Andrew Bresticker Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Jason Cooper Cc: Paul Burton Cc: Qais Yousef Cc: John Crispin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8139/ Signed-off-by: Ralf Baechle

clocksource: mips-gic: Combine with GIC clockevent driver

2014-11-24T06:45:15+00:00

Combine the GIC clocksource driver with the GIC clockevent driver from arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate Kconfig symbol. Signed-off-by: Andrew Bresticker Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Jason Cooper Cc: Andrew Bresticker Cc: Paul Burton Cc: Qais Yousef Cc: John Crispin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8132/ Signed-off-by: Ralf Baechle

MIPS: Add hook to get C0 performance counter interrupt

2014-11-24T06:44:53+00:00

The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by: Andrew Bresticker Reviewed-by: Qais Yousef Tested-by: Qais Yousef Cc: Thomas Gleixner Cc: Jason Cooper Cc: Andrew Bresticker Cc: Jeffrey Deans Cc: Markos Chandras Cc: Paul Burton Cc: Qais Yousef Cc: Jonas Gorski Cc: John Crispin Cc: David Daney Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7805/ Signed-off-by: Ralf Baechle

MIPS: MT: Remove SMTC support

2014-05-23T22:07:01+00:00

Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle

MIPS: Always register R4K clock when selected

2013-10-29T20:25:26+00:00

Always register the R4K clocksource when CONFIG_CSRC_R4K is selected, regardless of selected support for other clocksources. The kernel will select the best clocksource based on their ratings, making it safe to register R4K unconditionally and use it as a fallback should the kernel be run on a system where other selected clocksources are inoperable. Signed-off-by: Steven J. Hill Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6024/ Signed-off-by: Ralf Baechle

MIPS: Add new GIC clockevent driver.

2013-05-09T15:55:21+00:00

Add new clockevent driver that uses the counter present on the MIPS Global Interrupt Controller. Signed-off-by: Raghu Gandham Signed-off-by: Steven J. Hill

MIPS: Formatting clean-ups for clocksources.

2013-05-09T15:55:21+00:00

Various whitespace and #ifdef removals for GIC and R4K clocksources. Signed-off-by: Steven J. Hill