kernel/linux.git/arch/mips/include/asm/bmips.h, branch v6.19.11

mips: Replace ASSEMBLY with ASSEMBLER in the mips headers

2025-08-29T20:34:29+00:00

While the GCC and Clang compilers already define __ASSEMBLER__ automatically when compiling assembler code, __ASSEMBLY__ is a macro that only gets defined by the Makefiles in the kernel. Defining such a macro was necessary in the early days of the kernel, since GCC only started providing __ASSEMBLER__ since version 3.0 in 2000 (see https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=f8f769ea4e69 ). However, having two macros can be very confusing nowadays for the developers when switching between userspace and kernelspace coding, or when dealing with uapi headers that should use __ASSEMBLER__ instead. So let's now standardize on the __ASSEMBLER__ macro that is provided by the compilers. This is almost a completely mechanical patch (done with a simple "sed -i" statement), with just one comment tweaked manually in arch/mips/include/asm/cpu.h (that was missing some underscores). Cc: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Maciej W. Rozycki Signed-off-by: Thomas Huth Signed-off-by: Thomas Bogendoerfer

mips: bmips: rework and cache CBR addr handling

2024-06-27T08:44:24+00:00

Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in setup.c for each arch to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Acked-by: Florian Fainelli Signed-off-by: Christian Marangi Signed-off-by: Thomas Bogendoerfer

MIPS: bmips: mark exception vectors as char arrays

2019-10-24T04:07:28+00:00

The vectors span more than one byte, so mark them as arrays. Fixes the following build error when building when using GCC 8.3: In file included from ./include/linux/string.h:19, from ./include/linux/bitmap.h:9, from ./include/linux/cpumask.h:12, from ./arch/mips/include/asm/processor.h:15, from ./arch/mips/include/asm/thread_info.h:16, from ./include/linux/thread_info.h:38, from ./include/asm-generic/preempt.h:5, from ./arch/mips/include/generated/asm/preempt.h:1, from ./include/linux/preempt.h:81, from ./include/linux/spinlock.h:51, from ./include/linux/mmzone.h:8, from ./include/linux/bootmem.h:8, from arch/mips/bcm63xx/prom.c:10: arch/mips/bcm63xx/prom.c: In function 'prom_init': ./arch/mips/include/asm/string.h:162:11: error: '__builtin_memcpy' forming offset [2, 32] is out of the bounds [0, 1] of object 'bmips_smp_movevec' with type 'char' [-Werror=array-bounds] __ret = __builtin_memcpy((dst), (src), __len); \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/bcm63xx/prom.c:97:3: note: in expansion of macro 'memcpy' memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); ^~~~~~ In file included from arch/mips/bcm63xx/prom.c:14: ./arch/mips/include/asm/bmips.h:80:13: note: 'bmips_smp_movevec' declared here extern char bmips_smp_movevec; Fixes: 18a1eef92dcd ("MIPS: BMIPS: Introduce bmips.h") Signed-off-by: Jonas Gorski Reviewed-by: Florian Fainelli Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: Ralf Baechle Cc: James Hogan

MIPS: bmips: use generic dma noncoherent ops

2018-06-24T16:27:27+00:00

Provide phys_to_dma/dma_to_phys helpers, and the special arch_sync_dma_for_cpu_all hook, everything else is generic Signed-off-by: Christoph Hellwig Patchwork: https://patchwork.linux-mips.org/patch/19550/ Signed-off-by: Paul Burton Cc: Florian Fainelli Cc: David Daney Cc: Kevin Cernekee Cc: Jiaxun Yang Cc: Tom Bogendoerfer Cc: Huacai Chen Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org

MIPS: SMP: Constify smp ops

2017-08-29T13:21:50+00:00

smp_ops providers do not modify their ops structures, so they should be made const for robustness. Since currently the MIPS kernel is not mapped with memory protection, this does not in itself provide any security benefit, but it still makes sense to make this change. There are also slight code size efficincies from the structure being made read-only, saving 128 bytes of kernel text on a pistachio_defconfig. Before: text data bss dec hex filename 7187239 1772752 470224 9430215 8fe4c7 vmlinux After: text data bss dec hex filename 7187111 1772752 470224 9430087 8fe447 vmlinux Signed-off-by: Matt Redfearn Cc: Sebastian Andrzej Siewior Cc: Arnd Bergmann Cc: Marcin Nowakowski Cc: Bart Van Assche Cc: Masahiro Yamada Cc: Huacai Chen Cc: Paul Gortmaker Cc: Kevin Cernekee Cc: Thomas Gleixner Cc: Doug Ledford Cc: James Hogan Cc: Joe Perches Cc: Florian Fainelli Cc: Ingo Molnar Cc: Paul Burton Cc: Andrew Morton Cc: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16784/ Signed-off-by: Ralf Baechle

MIPS: BMIPS: Add early CPU initialization code

2016-05-13T12:01:55+00:00

Port the stblinux-3.3 code to perform a bunch of CPU-specific initialization, make it compatible with run-time detection of the CPU, and unroll the brcmstb-specific macros: BDEV_RB(), BDEV_UNSET. The "pref 30" disabling is done as a quirk. This is a preliminary change to allow the use of the "rotr" instruction gated by cpu_has_rixi. Signed-off-by: Florian Fainelli Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12504/ Signed-off-by: Ralf Baechle

MIPS: BMIPS: Move post DMA flush implementation to common header

2015-04-08T21:52:32+00:00

arch/mips/include/asm/mach-bmips/dma-coherence.h contains the plat_post_dma_flush implementation which is not specific to mach-bmips, but required for all BMIPS-based systems. Move plat_post_dma_flush to arch/mips/include/asm/bmips.h, rename it to bmips_post_dma_flush such that other platforms like bcm63xx can utilize it. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/9724/ Signed-off-by: Ralf Baechle

MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask

2014-11-24T06:45:11+00:00

On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1 input, generating spurious IRQs. In this case we want the platform code to be able to mask it off. Signed-off-by: Kevin Cernekee Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8163/ Signed-off-by: Ralf Baechle

MIPS: BMIPS: add a smp ops registration helper

2014-01-22T19:18:52+00:00

Add a helper similar to the generic register_XXX_smp_ops() for bmips. Register SMP UP ops in case of BMIPS32/3300. Signed-off-by: Jonas Gorski Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6248/

MIPS: BMIPS: change compile time checks to runtime checks

2014-01-22T19:18:51+00:00

Allow building for all bmips cpus at the same time by changing ifdefs to checks for the cpu type, or adding appropriate checks to the assembly. Since BMIPS43XX and BMIPS5000 require different IPI implementations, split the SMP ops into one for each, so the runtime overhead is only at registration time for them. Signed-off-by: Jonas Gorski Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6241/