kernel/linux.git/arch/mips/generic/Makefile, branch v6.6.133

MIPS: generic: Add support for Ingenic SoCs

2020-09-18T14:33:59+00:00

Add support for Ingenic SoCs in arch/mips/generic/. The Kconfig changes are here to ensure that it is possible to compile either a generic kernel that supports Ingenic SoCs, or a Ingenic-only kernel, both using the same code base, to avoid duplicated code. Signed-off-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

MIPS: kexec: Use prepare method from Generic for UHI platforms

2018-09-22T17:32:34+00:00

Out-of-tree platforms may not be based on Generic as shown in customer communication. Share the prepare method with all using UHI boot protocol, and put into machine_kexec.c. The benefit is that, when having kexec_args related problems, developers will naturally look into machine_kexec.c, where "CONFIG_UHI_BOOT" will be found, prompting them to add "select UHI_BOOT" to the platform Kconfig. It would otherwise require a lot debugging or online searching to be aware that the solution is in Generic code. Tested-by: Rachel Mozes Reported-by: Rachel Mozes Signed-off-by: Dengcheng Zhu Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/20569/ Cc: pburton@wavecomp.com Cc: ralf@linux-mips.org Cc: linux-mips@linux-mips.org

MIPS: generic: Add support for Microsemi Ocelot

2018-03-21T23:33:10+00:00

Introduce support for the MIPS based Microsemi Ocelot SoCs. Signed-off-by: Alexandre Belloni Cc: Ralf Baechle Cc: Allan Nielsen Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18858/ [jhogan@kernel.org: update ocelot_defconfig specification] Signed-off-by: James Hogan

MIPS: generic: Fix Makefile alignment

2018-02-05T10:39:56+00:00

Fix whitespace of generic platform Makefile so that obj-y values align. Fixes: f2d0b0d5c171 ("MIPS: ranchu: Add Ranchu as a new generic-based board") Signed-off-by: James Hogan Reviewed-by: Paul Burton Reviewed-by: Matt Redfearn Cc: Ralf Baechle Cc: Miodrag Dinic Cc: Goran Ferenc Cc: Aleksandar Markovic Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18582/

MIPS: ranchu: Add Ranchu as a new generic-based board

2018-01-22T20:47:34+00:00

Provide amendments to the MIPS generic platform framework so that the new generic-based board Ranchu can be chosen to be built. The Ranchu board is intended to be used by Android emulator. The name "Ranchu" originates from Android development community. "Goldfish" and "Ranchu" are terms used for two generations of virtual boards used by Android emulator. The name "Ranchu" is a newer one among the two, and this patch deals with Ranchu. However, for historical reasons, some devices/drivers still contain the name "Goldfish". MIPS Ranchu machine includes a number of Goldfish devices. The support for Virtio devices is also included. Ranchu board supports up to 16 Virtio devices which can be attached using Virtio MMIO Bus. This is summarized in the following picture: ABUS ||----MIPS CPU || | IRQs ||----Goldfish PIC------------(32)-------- || | | | | | | | | | ||----Goldfish TTY------ | | | | | | | | || | | | | | | | | ||----Goldfish RTC-------- | | | | | | | || | | | | | | | ||----Goldfish FB----------- | | | | | | || | | | | | | ||----Goldfish Events--------- | | | | | || | | | | | ||----Goldfish Audio------------ | | | | || | | | | ||----Goldfish Battery------------ | | | || | | | ||----Android PIPE------------------ | | || | | ||----Virtio MMIO Bus | | || | | | | | || | | (virtio-block)--------- | || (16) | | || | (virtio-net)------------------ Device Tree is created on the QEMU side based on the information about devices IO map and IRQ numbers. Kernel will load this DTB using UHI boot protocol DTB handover mode. Signed-off-by: Miodrag Dinic Signed-off-by: Goran Ferenc Signed-off-by: Aleksandar Markovic Reviewed-by: James Hogan Cc: Ralf Baechle Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18138/ Signed-off-by: James Hogan

Update MIPS email addresses

2017-11-03T16:02:30+00:00

MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who: - Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year. - Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list. - Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej). - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself. New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead. Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address. Signed-off-by: Paul Burton Cc: Deng-Cheng Zhu Cc: Deng-Cheng Zhu Acked-by: Dengcheng Zhu Cc: Matt Redfearn Cc: Matt Redfearn Acked-by: Matt Redfearn Cc: Andrew Morton Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Signed-off-by: Linus Torvalds

MIPS: generic/yamon-dt: Pull YAMON DT shim code out of SEAD-3 board

2017-06-28T10:22:40+00:00

In preparation for supporting other YAMON-using boards (Malta) & sharing code to translate information from YAMON into device tree properties, pull the code doing so for the kernel command line, system memory & serial configuration out of the SEAD-3 board code. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16181/ Signed-off-by: Ralf Baechle

MIPS: generic/kexec: add support for a DTB passed in a separate buffer

2017-01-03T15:34:46+00:00

Signed-off-by: Marcin Nowakowski Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14615/ Signed-off-by: Ralf Baechle

MIPS: generic: Convert SEAD-3 to a generic board

2016-10-06T16:04:20+00:00

Convert the MIPS SEAD-3 board support to be a generic board, supported by generic kernels. Because the SEAD-3 boot protocol was defined long ago and we don't want to force a switch to the UHI protocol, SEAD-3 is added as a legacy board which is detected by reading the REVISION register. This may technically not be a valid memory read & future work will include attempting to handle that gracefully. In practice since SEAD-3 is the only legacy board supported by the generic kernel so far the read will only happen on SEAD-3 boards, and even once Malta is converted the same REVISION register exists there too. Other boards such as Boston, Ci20 & Ci40 will use the UHI boot protocol & thus not run any of the legacy board detect functions. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14354/ Signed-off-by: Ralf Baechle