Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y 2026-02-10T11:31:06+00:00 2026-02-10T11:31:06+00:00 George Guo dongtai.guo@linux.dev 2026-02-10T11:31:06+00:00 urn:sha1:48543c4283e76d561d11b9955222b1a3054abdb9 Check the CPUCFG2_SCQ bit to determine if the current CPU supports the SC.Q instruction. Reviewed-by: Hengqi Chen <hengqi.chen@gmail.com> Tested-by: Hengqi Chen <hengqi.chen@gmail.com> Co-developed-by: Yangyang Lian <lianyangyang@kylinos.cn> Signed-off-by: Yangyang Lian <lianyangyang@kylinos.cn> Signed-off-by: George Guo <guodongtai@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2025-12-08T10:09:17+00:00 Huacai Chen chenhuacai@loongson.cn 2025-12-08T10:09:17+00:00 urn:sha1:dd55dd0d7e5ddceb6df451dac208af38609d1963 Adjust memory management for both 32BIT and 64BIT, including: address space definition, DMW CSR definition, page table bits definition, boot time detection of VA/PA bits, page table init, tlb exception handling, copy_page/clear_page/dump_tlb libraries, etc. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Yawei Li <liyawei@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2025-11-10T00:37:06+00:00 Huacai Chen chenhuacai@loongson.cn 2025-11-09T08:02:00+00:00 urn:sha1:f28abb9f96e65a28d46885afd6b70cfc4d5df5a2 LoongArch's MSG interrupt features are used across multiple subsystems. Clarify these features to avoid misuse, existing users will be adjusted if necessary. MSGINT: Infrastructure, means the CPU core supports message interupts. Indicated by CPUCFG1.MSGINT. AVECINT: AVEC interrupt controller based on MSGINT, means the CPU chip supports direct message interrupts. Indicated by IOCSR.FEATURES.DMSI. REDIRECTINT: REDIRECT interrupt controller based on MSGINT and AVECINT, means the CPU chip supports redirect message interrupts. Indicated by IOCSR.FEATURES.RMSI. For example: Loongson-3A5000/3C5000 doesn't support MSGINT/AVECINT/REDIRECTINT; Loongson-3A6000 supports MSGINT but doesn't support AVECINT/REDIRECTINT; Loongson-3C6000 supports MSGINT/AVECINT/REDIRECTINT. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2024-09-24T07:32:20+00:00 Jiaxun Yang jiaxun.yang@flygoat.com 2024-09-24T07:32:20+00:00 urn:sha1:34e3c4500cdc06094b37a41b622598098308ba8f Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel resilience to different core implementations. BTW, IOCSR register definition appears to be a platform-specific spec instead of an architecture spec, even for the Loongson CPUs there is no guarantee that IOCSR will always present. Thus it's dangerous to perform IOCSR probing without checking CPU type and instruction availability. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2024-08-23T18:40:27+00:00 Huacai Chen chenhuacai@loongson.cn 2024-08-23T10:39:33+00:00 urn:sha1:843ed9317be1d0c3f4245418644fc7e55f465419 Add architectural preparation for AVEC irqchip, including: 1. CPUCFG feature bits definition for AVEC; 2. Detection of AVEC irqchip in cpu_probe(); 3. New IPI type definition (IPI_CLEAR_VECTOR) for AVEC; 4. Provide arch_probe_nr_irqs() for large NR_IRQS; 5. Other related changes about the number of interrupts. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20240823103936.25092-2-zhangtianyang@loongson.cn 2023-06-29T12:58:44+00:00 Huacai Chen chenhuacai@loongson.cn 2023-06-29T12:58:44+00:00 urn:sha1:01158487af60cd3915e8c31924144caf29cb0767 Loongson-3A6000 and newer processors have hardware page table walker (PTW) support. PTW can handle all fastpaths of TLBI/TLBL/TLBS/TLBM exceptions by hardware, software only need to handle slowpaths (page faults). BTW, PTW doesn't append _PAGE_MODIFIED for page table entries, so we change pmd_dirty() and pte_dirty() to also check _PAGE_DIRTY for the "dirty" attribute. Signed-off-by: Liang Gao <gaoliang@loongson.cn> Signed-off-by: Jun Yi <yijun@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2023-04-18T11:38:58+00:00 Huacai Chen chenhuacai@loongson.cn 2023-04-18T11:38:58+00:00 urn:sha1:df830336045db1246d3245d3737fee9939c5f731 Not all LoongArch processors support CRC32 instructions. This feature is indicated by CPUCFG1.CRC32 (Bit25) but it is wrongly defined in the previous versions of the ISA manual (and so does in loongarch.h). The CRC32 feature is set unconditionally now, so fix it. BTW, expose the CRC32 feature in /proc/cpuinfo. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2022-10-12T08:36:14+00:00 Huacai Chen chenhuacai@loongson.cn 2022-10-12T08:36:14+00:00 urn:sha1:b61a40afca164a9bd066f749beff3bf209c5e209 Current cache probe and flush methods have some drawbacks: 1, Assume there are 3 cache levels and only 3 levels; 2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive. However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are all valid. So, refactor the cache probe and flush methods to adapt more types of cache hierarchy. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2022-06-03T12:09:28+00:00 Huacai Chen chenhuacai@loongson.cn 2022-05-31T10:04:11+00:00 urn:sha1:f2ac457a61389b7769aad8295027cbe0f91c5b80 Add common headers (CPU definition and address space layout) for basic LoongArch support. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>