<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/arch/csky/include/asm/cacheflush.h, branch v6.12.80</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2021-02-27T14:04:14+00:00</updated>
<entry>
<title>csky: Fixup compile error</title>
<updated>2021-02-27T14:04:14+00:00</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2021-02-27T14:00:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6607aa6f6b68fc9b5955755f1b1be125cf2a9d03'/>
<id>urn:sha1:6607aa6f6b68fc9b5955755f1b1be125cf2a9d03</id>
<content type='text'>
: error: C++ style comments are not allowed in ISO C90
 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
 ^
error: (this will be reported only once per input file)

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
</content>
</entry>
<entry>
<title>csky: Add flush_icache_mm to defer flush icache all</title>
<updated>2020-02-21T07:43:24+00:00</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2020-01-31T12:33:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=997153b9a75c08d545ad45e6f8ceb432435d2425'/>
<id>urn:sha1:997153b9a75c08d545ad45e6f8ceb432435d2425</id>
<content type='text'>
Some CPUs don't support icache.va instruction to maintain the whole
smp cores' icache. Using icache.all + IPI casue a lot on performace
and using defer mechanism could reduce the number of calling icache
_flush_all functions.

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
</content>
</entry>
<entry>
<title>csky: Cache and TLB routines</title>
<updated>2018-10-25T15:36:19+00:00</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-09-05T06:25:10+00:00</published>
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<id>urn:sha1:00a9730e1007c6cc87a7c78af2f24a4105d616ee</id>
<content type='text'>
This patch adds cache and tlb sync codes for abiv1 &amp; abiv2.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
</feed>
