kernel/linux.git/arch/csky/abiv2/cacheflush.c, branch v6.4

csky: mmu: Prevent spurious page faults

2023-04-13T06:36:14+00:00

C-SKY MMU would pre-fetch invalid pte entries, and it could work with flush_tlb_fix_spurious_fault, but the additional page fault exceptions would reduce performance. So flushing the entry of the TLB would prevent the following spurious page faults. Here is the test code: define DATA_LEN 4096 define COPY_NUM (504*100) unsigned char src[DATA_LEN*COPY_NUM] = {0}; unsigned char dst[DATA_LEN*COPY_NUM] = {0}; unsigned char func_src[DATA_LEN*COPY_NUM] = {0}; unsigned char func_dst[DATA_LEN*COPY_NUM] = {0}; void main(void) { int j; for (j = 0; j < COPY_NUM; j++) memcpy(&dst[j*DATA_LEN], &src[j*DATA_LEN], 4); } perf stat -e page-faults ./main.elf The amount of page fault traps would be reduced in half with the patch. Signed-off-by: Guo Ren Signed-off-by: Guo Ren

csky: Fixup update_mmu_cache called with user io mapping

2021-01-12T01:52:41+00:00

The function update_mmu_cache could be called by user-io mapping. There is no space of struct page in mem_map for the pte. Just ignore the user-io mmaping in update_mmu_cache. Signed-off-by: Guo Ren

csky: Add flush_icache_mm to defer flush icache all

2020-02-21T07:43:24+00:00

Some CPUs don't support icache.va instruction to maintain the whole smp cores' icache. Using icache.all + IPI casue a lot on performace and using defer mechanism could reduce the number of calling icache _flush_all functions. Signed-off-by: Guo Ren

csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)

2020-02-21T07:43:24+00:00

Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache. As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache(). Signed-off-by: Guo Ren

csky: Remove unnecessary flush_icache_* implementation

2020-02-21T07:43:24+00:00

The abiv2 CPUs are all PIPT cache, so there is no need to implement flush_icache_page function. The function flush_icache_user_range hasn't been used, so just remove it. The function flush_cache_range is not necessary for PIPT cache when tlb mapping changed. Signed-off-by: Guo Ren

csky: Fixup wrong update_mmu_cache implementation

2019-04-22T05:44:57+00:00

In our stress test, we found some crash problem caused by: if (!(vma->vm_flags & VM_EXEC)) return; in update_mmu_cache(). Seems current update_mmu_cache implementation is wrong and we retread to the conservative implementation. Also the usage of kmap_atomic in update_mmu_cache is risky, page-virtual may be scheduled out and changed, so we must use preempt_disable & pagefault_disable which is called by kmap_atomic(). Signed-off-by: Guo Ren Cc: Arnd Bergmann

csky: Cache and TLB routines

2018-10-25T15:36:19+00:00

This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren Reviewed-by: Arnd Bergmann