kernel/linux.git/arch/arm64/boot, branch v7.0-rc7

arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers

2026-03-06T12:15:21+00:00

SPI interrupts are in the range 0-987. Extended SPI interrupts should use GIC_ESPI, instead of abusing GIC_SPI with a manual offset of 4064. Fixes: 63500d12cf76d003 ("arm64: dts: renesas: Add R8A78000 SoC support") Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/1f9dd274720ea1b66617a5dd84f76c3efc829dc8.1772641415.git.geert+renesas@glider.be

arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2

2026-03-06T12:15:02+00:00

The default settings for the Versa3 device on the Renesas RZ/G3S SMARC SoM board have PLL2 disabled. PLL2 was later enabled together with audio support, as it is required to support both 44.1 kHz and 48 kHz audio. With PLL2 enabled, it was observed that Linux occasionally either hangs during boot (the last log message being related to the I2C probe) or randomly crashes. This was mainly reproducible on cold boots. During debugging, it was also noticed that the Unicode replacement character (�) sometimes appears on the serial console. Further investigation traced this to the configuration applied through the Versa3 register at offset 0x1c, which controls PLL enablement. The appearance of the Unicode replacement character suggested an issue with the SoC reference clock. The RZ/G3S reference clock is provided by the Versa3 clock generator (REF output). After checking with the Renesas Versa3 hardware team, it was found that this is related to the PLL2 lock bit being set through the renesas,settings DT property. The PLL lock bit must be set to avoid unstable clock output from the PLL. However, due to the Versa3 hardware design, when a PLL lock bit is set, all outputs (including the REF clock) are temporarily disabled until the configured PLLs become stable. As an alternative, the bypass bit can be used. This does not interrupt the PLL2 output or any other Versa3 outputs, but it may result in temporary instability on PLL2 output while the configuration is applied. Since PLL2 feeds only the audio path and audio is not used during early boot, this is acceptable and does not affect system boot. Drop the PLL2 lock bit and set the bypass bit instead. This has been tested with more than 1000 cold boots. Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

arm64: dts: renesas: r9a09g087: Fix CPG register region sizes

2026-03-06T12:15:02+00:00

The CPG register regions were incorrectly sized. Update them to match the actual hardware specification: - First region (0x80280000): 0x1000 -> 0x10000 (64kiB) - Second region (0x81280000): 0x9000 -> 0x10000 (64kiB) Fixes: 4b3d31f0b81fe ("arm64: dts: renesas: Add initial SoC DTSI for the RZ/N2H SoC") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260213131742.3606334-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

arm64: dts: renesas: r9a09g077: Fix CPG register region sizes

2026-03-06T12:15:02+00:00

The CPG register regions were incorrectly sized. Update them to match the actual hardware specification: - First region (0x80280000): 0x1000 -> 0x10000 (64kiB) - Second region (0x81280000): 0x9000 -> 0x10000 (64kiB) Fixes: d17b34744f5e4 ("arm64: dts: renesas: Add initial support for the Renesas RZ/T2H SoC") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260213131742.3606334-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes

2026-03-06T12:15:02+00:00

The HW user manual for the Renesas RZ/V2H(P) SoC (a.k.a r9a09g057) states that only WDT1 is supposed to be accessed by the CA55 cores. WDT0 is supposed to be used by the CM33 core, WDT2 is supposed to be used by the CR8 core 0, and WDT3 is supposed to be used by the CR8 core 1. Remove wdt{0,2,3} from the SoC specific device tree to make it compliant with the specification from the HW manual. This change is harmless as there are currently no users of the wdt{0,2,3} device tree nodes, only the wdt1 node is actually used. Fixes: 095105496e7d ("arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes") Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260203124247.7320-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven

arm64: dts: renesas: rzv2-evk-cn15-sd: Add ramp delay for SD0 regulator

2026-03-06T12:15:02+00:00

Set an appropriate ramp delay for the SD0 I/O voltage regulator in the CN15 SD overlay to make UHS-I voltage switching reliable during card initialization. This issue was observed on the RZ/V2H EVK, while the same UHS-I cards worked on the RZ/V2N EVK without problems. Adding the ramp delay makes the behavior consistent and avoids SD init timeouts. Before this change SD0 could fail with: mmc0: error -110 whilst initialising SD card With the delay in place UHS-I cards enumerate correctly: mmc0: new UHS-I speed SDR104 SDXC card at address aaaa mmcblk0: mmc0:aaaa SR64G 59.5 GiB mmcblk0: p1 Fixes: 3d6c2bc7629c8 ("arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260123225957.1007089-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

arm64: dts: renesas: rzt2h-n2h-evk: Add ramp delay for SD0 card regulator

2026-03-06T12:15:02+00:00

Add a ramp delay of 60 uV/us to the vqmmc_sdhi0 voltage regulator to fix UHS-I SD card detection failures. Measurements on CN78 pin 4 showed the actual voltage ramp time to be 21.86ms when switching between 3.3V and 1.8V. A 25ms ramp delay has been configured to provide adequate margin. The calculation is based on the voltage delta of 1.5V (3.3V - 1.8V): 1500000 uV / 60 uV/us = 25000 us (25ms) Prior to this patch, UHS-I cards failed to initialize with: mmc0: error -110 whilst initialising SD card After this patch, UHS-I cards are properly detected on SD0: mmc0: new UHS-I speed SDR104 SDXC card at address aaaa mmcblk0: mmc0:aaaa SR64G 59.5 GiB Fixes: d065453e5ee09 ("arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260123225957.1007089-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2026-02-11T05:11:08+00:00

Pull SoC devicetree updates from Arnd Bergmann: "There are a handful of new SoCs this time, all of these are more or less related to chips in a wider family: - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first widely available RVA23 implementation. Note that this is entirely unrelated with the similarly named Texas Instruments K3 chip family that follwed the TI Keystone2 SoC. - The Realtek Kent family of SoCs contains three chip models rtd1501s, rtd1861b and rtd1920s, and is related to their earlier Set-top-box and NAS products such as rtd1619, but is built on newer Arm Cortex-A78 cores. - The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm Cortex-A720 generation. This one is used in the Fairphone Gen 6 - Qualcomm Kaanapali is a new SoC based around eight high performance Oryon CPU cores - NXP i.MX8QP and i.MX952 are both feature reduced versions of chips we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU cores and I/O interfaces. As part of a cleanup, a number of SoC specific devicetree files got removed because they did not have a single board using the .dtsi files and they were never compile tested as a result: Samsung s3c6400, ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/ r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715. All of these could be restored easily if a new board gets merged. Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only machine, as all remaining users are assumed to be using ACPI based firmware. A relatively small number of 43 boards get added this time, and almost all of them for arm64. Aside from the reference boards for the newly added SoCs, this includes: - Three server boards use 32-bit ASpeed BMCs - One more reference board for 32-bit Microchip LAN9668 - 64-bit Arm single-board computers based on Amlogic s905y4, CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020, NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588 - Two mobile phones using Snapdragon 845 - A gaming device and a NAS box, both based on Rockchips rk356x On top of the newly added boards and SoCs, there is a lot of background activity going into cleanups, in particular towards getting a warning-free dtc build, and the usual work on adding support for more hardware on the previously added machines" * tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits) dt-bindings: intel: Add Agilex eMMC support arm64: dts: socfpga: agilex: add emmc support arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node ARM: dts: socfpga: fix dtbs_check warning for fpga-region ARM: dts: socfpga: add #address-cells and #size-cells for sram node dt-bindings: altera: document syscon as fallback for sys-mgr arm64: dts: altera: Use lowercase hex dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes arm64: dts: socfpga: agilex5: add support for modular board dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: agilex5: Add dma-coherent property arm64: dts: realtek: Add Kent SoC and EVB device trees dt-bindings: arm: realtek: Add Kent Soc family compatibles ARM: dts: samsung: Drop s3c6400.dtsi ARM: dts: nuvoton: Minor whitespace cleanup MAINTAINERS: Add Falcon DB arm64: dts: a7k: add COM Express boards ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi arm64: dts: rockchip: Fix rk3588 PCIe range mappings ...

Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2026-02-10T22:01:40+00:00

Pull irq chip driver updates from Thomas Gleixner: - Add support for the Renesas RZ/V2N SoC - Add a new driver for the Renesas RZ/[TN]2H SoCs - Preserve the register state of the RISCV APLIC interrupt controller accross suspend/resume - Reinitialize the RISCV IMSIC registers after suspend/resume - Make the various Loongson interrupt chip drivers 32/64-bit aware - Handle the number of hardware interrupts in the SIFIVE PLIC driver correctly The hardware interrupt 0 is reserved which resulted in inconsistent accounting. That went unnoticed as the off by one is only noticable when the number of device interrupts is a multiple of 32 - The usual device tree updates, cleanups and improvements all over the place * tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits) irqchip/gic-v5: Fix spelling mistake "ouside" -> "outside" dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC irqchip/sifive-plic: Handle number of hardware interrupts correctly irqchip/aspeed-scu-ic: Remove unused variable mask irqchip/ti-sci-intr: Allow parsing interrupt-types per-line dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types irqchip/renesas-rzv2h: Add suspend/resume support irqchip/aslint-sswi: Fix error check of of_io_request_and_map() result irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT irqchip/riscv-aplic: Preserve APLIC states across suspend/resume irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit arm64: dts: renesas: r9a09g087: Add ICU support arm64: dts: renesas: r9a09g077: Add ICU support irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver ...

Merge tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

2026-02-04T07:39:08+00:00

SoCFPGA DTS updates for v6.20, version 3 - dt-bindings updates: - Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board - Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board - Move entries in intel,socfpga.yaml into altera.yaml - Add syscon as a fallback for sys-mgr - Add dma-cohrerent property for Agilex5 NAND and DMA - Add support for the Agilex5 modular board - Add IOMMUS property for ethernet nodes for Agilex5 - Use lowercase hex for dts files - Add #address-cells and #size-cells for sram - Fix dtbs_check warning for fpga-region - Move dma controller node for Agilex5 under simple-bus - Add support for the Agilex eMMC daughter board * tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: dt-bindings: intel: Add Agilex eMMC support arm64: dts: socfpga: agilex: add emmc support arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node ARM: dts: socfpga: fix dtbs_check warning for fpga-region ARM: dts: socfpga: add #address-cells and #size-cells for sram node dt-bindings: altera: document syscon as fallback for sys-mgr arm64: dts: altera: Use lowercase hex dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes arm64: dts: socfpga: agilex5: add support for modular board dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: agilex5: Add dma-coherent property Signed-off-by: Arnd Bergmann