kernel/linux.git/arch/arm/boot/dts/intel, branch master

Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2026-02-11T05:11:08+00:00

Pull SoC devicetree updates from Arnd Bergmann: "There are a handful of new SoCs this time, all of these are more or less related to chips in a wider family: - SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first widely available RVA23 implementation. Note that this is entirely unrelated with the similarly named Texas Instruments K3 chip family that follwed the TI Keystone2 SoC. - The Realtek Kent family of SoCs contains three chip models rtd1501s, rtd1861b and rtd1920s, and is related to their earlier Set-top-box and NAS products such as rtd1619, but is built on newer Arm Cortex-A78 cores. - The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm Cortex-A720 generation. This one is used in the Fairphone Gen 6 - Qualcomm Kaanapali is a new SoC based around eight high performance Oryon CPU cores - NXP i.MX8QP and i.MX952 are both feature reduced versions of chips we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU cores and I/O interfaces. As part of a cleanup, a number of SoC specific devicetree files got removed because they did not have a single board using the .dtsi files and they were never compile tested as a result: Samsung s3c6400, ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/ r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715. All of these could be restored easily if a new board gets merged. Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only machine, as all remaining users are assumed to be using ACPI based firmware. A relatively small number of 43 boards get added this time, and almost all of them for arm64. Aside from the reference boards for the newly added SoCs, this includes: - Three server boards use 32-bit ASpeed BMCs - One more reference board for 32-bit Microchip LAN9668 - 64-bit Arm single-board computers based on Amlogic s905y4, CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s - Carrier board for SOMs using Intel agilex5, Marvell Armada 7020, NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588 - Two mobile phones using Snapdragon 845 - A gaming device and a NAS box, both based on Rockchips rk356x On top of the newly added boards and SoCs, there is a lot of background activity going into cleanups, in particular towards getting a warning-free dtc build, and the usual work on adding support for more hardware on the previously added machines" * tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits) dt-bindings: intel: Add Agilex eMMC support arm64: dts: socfpga: agilex: add emmc support arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node ARM: dts: socfpga: fix dtbs_check warning for fpga-region ARM: dts: socfpga: add #address-cells and #size-cells for sram node dt-bindings: altera: document syscon as fallback for sys-mgr arm64: dts: altera: Use lowercase hex dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes arm64: dts: socfpga: agilex5: add support for modular board dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: agilex5: Add dma-coherent property arm64: dts: realtek: Add Kent SoC and EVB device trees dt-bindings: arm: realtek: Add Kent Soc family compatibles ARM: dts: samsung: Drop s3c6400.dtsi ARM: dts: nuvoton: Minor whitespace cleanup MAINTAINERS: Add Falcon DB arm64: dts: a7k: add COM Express boards ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi arm64: dts: rockchip: Fix rk3588 PCIe range mappings ...

ARM: dts: socfpga: fix dtbs_check warning for fpga-region

2026-01-30T15:27:12+00:00

soc (simple-bus): base_fpga_region: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml base_fpga_region (fpga-region): $nodename:0: 'base_fpga_region' does not match '^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/fpga/fpga-region.yaml Signed-off-by: Dinh Nguyen

ARM: dts: socfpga: add #address-cells and #size-cells for sram node

2026-01-30T15:27:12+00:00

Add #address-cells and #size-cells for sram node to fix below DTB_CHECK warnings: socfpga_arria5_socdk.dtb: sram@ffff0000 (mmio-sram): '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml Signed-off-by: Dinh Nguyen

ARM: dts: ixp4xx: Fix up Actiontec MI424WR DTS files

2025-12-15T20:15:36+00:00

The KS8995 switch was unconditionally wired to EthC (eth1) on both MI424WR variants, this is wrong: the D revision has the switch connected to EthB (eth0) so pull this assingment out of the generic MI424WR DTSI file and make it a property of the respective variants instead. Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20251211-ixp4xx-actiontec-dts-fix-v1-1-97af8e79d474@kernel.org Signed-off-by: Krzysztof Kozlowski

ARM: dts: socfpga: add Enclustra SoM dts files

2025-10-20T16:26:34+00:00

Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch Signed-off-by: Dinh Nguyen

ARM: dts: socfpga: removal of generic PE1 dts

2025-10-20T16:25:43+00:00

Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate, the hardware is covered by the combination of Enclustra's .dtsi files. The older .dts was limited to only the case of having an Enclustra Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This functionality is provided also by the generic Enclustra dtsi and dts files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since both .dts files cover the same, the older one is to e replaced in favor of the more modularized approach. Signed-off-by: Lothar Rubusch Acked-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen

ARM: dts: socfpga: add Mercury AA1 variants

2025-10-20T16:24:03+00:00

Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel Arria10. This is a flexible approach to allow for combining SoM with carrier board .dtsi and boot-mode .dtsi in a device-tree file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch Signed-off-by: Dinh Nguyen

ARM: dts: socfpga: add Enclustra Mercury+ SA2

2025-10-20T16:23:29+00:00

Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch Signed-off-by: Dinh Nguyen

ARM: dts: socfpga: add Enclustra Mercury SA1

2025-10-20T16:22:36+00:00

Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch Signed-off-by: Dinh Nguyen

ARM: dts: socfpga: add Enclustra base-board dtsi

2025-10-20T16:16:49+00:00

Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch Signed-off-by: Dinh Nguyen