kernel/linux.git/arch/arc/mm/cache.c, branch linux-4.16.y

ARCv2: cache: fix slc_entire_op: flush only instead of flush-n-inv

2018-01-17T20:26:52+00:00

slc_entire_op with OP_FLUSH command also invalidates it. This is a preventive fix as the current use of slc_entire_op is only with OP_FLUSH_N_INV where the invalidate is required. Signed-off-by: Eugeniy Paltsev [vgupta: fixed changelog] Signed-off-by: Vineet Gupta

ARC: mm: Decouple RAM base address from kernel link address

2017-09-01T18:26:27+00:00

[Needed for HSDK] Currently the first page of system (hence RAM base) is assumed to be @ CONFIG_LINUX_LINK_BASE, where kernel itself is linked. However is case of HSDK platform, for reasons explained in that patch, this is not true. kernel needs to be linked @ 0x9000_0000 while DDR is still wired at 0x8000_0000. To properly account for this 256M of RAM, we need to introduce a new option and base page frame accountiing off of it. Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta [vgupta: renamed CONFIG_KERNEL_RAM_BASE_ADDRESS => CONFIG_LINUX_RAM_BASE : simplified changelog]

ARCv2: IOC: Tighten up the contraints (specifically base / size alignment)

2017-09-01T18:26:26+00:00

[Needed for HSDK] - Currently IOC base is hardcoded to 0x8000_0000 which is default value of LINUX_LINK_BASE, but may not always be the case - IOC programming model imposes the constraint that IOC aperture size needs to be aligned to IOC base address, which we were not checking so far. Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta [vgupta: reworked the changelog]

ARCv2: SLC: provide a line based flush routine for debugging

2017-08-30T16:21:34+00:00

Signed-off-by: Vineet Gupta

ARC: set boot print log level to PR_INFO

2017-08-28T22:17:36+00:00

Some of the boot printing code had printk() w/o explicit log level. This patch introduces consistency allowing platforms to switch to less verbose console logging using cmdline. NPS400 with 4K CPUs needs to avoid the cpu info printing for faster bootup. Signed-off-by: Noam Camus Signed-off-by: Vineet Gupta

ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC

2017-08-04T08:26:35+00:00

PAE40 confiuration in hardware extends some of the address registers for TLB/cache ops to 2 words. So far kernel was NOT setting the higher word if feature was not enabled in software which is wrong. Those need to be set to 0 in such case. Normally this would be done in the cache flush / tlb ops, however since these registers only exist conditionally, this would have to be conditional to a flag being set on boot which is expensive/ugly - specially for the more common case of PAE exists but not in use. Optimize that by zero'ing them once at boot - nobody will write to them afterwards Cc: stable@vger.kernel.org #4.4+ Signed-off-by: Vineet Gupta

ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses

2017-08-04T08:26:34+00:00

It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner Without this patch, SLC flushes on HSDK (IOC disabled) were taking seconds. Cc: stable@vger.kernel.org #4.4+ Reported-by: Vladimir Kondratiev Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta [vgupta: PAR40 regs only written if PAE40 exist]

ARCv2: SLC: Make sure busy bit is set properly for region ops

2017-08-04T08:20:07+00:00

c70c473396cb "ARCv2: SLC: Make sure busy bit is set properly on SLC flushing" fixes problem for entire SLC operation where the problem was initially caught. But given a nature of the issue it is perfectly possible for busy bit to be read incorrectly even when region operation was started. So extending initial fix for regional operation as well. Signed-off-by: Alexey Brodkin Cc: stable@vger.kernel.org #4.10 Signed-off-by: Vineet Gupta

ARCv2: mm: Merge 2 updates to DC_CTRL for region flush

2017-05-02T23:16:07+00:00

ARCv2: mm: Implement cache region flush operations

2017-05-02T22:57:22+00:00

These are more efficient than the per-line ops Signed-off-by: Vineet Gupta