kernel/linux.git/arch/arc/include/asm/entry-compact.h, branch v4.20.9

ARC: [arcompact] entry.S: minor code movement

2018-07-09T18:25:45+00:00

This is a non functional code changw, which moves r25 restore from macro into the caller of macro Signed-off-by: Vineet Gupta

ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit

2017-08-28T22:17:36+00:00

Preserve eflags and gpa1 aux during entry/exit into kernel as these could be modified by kernel mode These registers used by compare exchange instructions. - GPA1 is used for compare value, - EFLAGS got bit reflects atomic operation response. EFLAGS is zeroed for each new user task so it won't get its parent value. Signed-off-by: Liav Rehana Signed-off-by: Noam Camus Signed-off-by: Vineet Gupta

Fix typos

2016-05-30T04:37:32+00:00

Signed-off-by: Andrea Gelmini Signed-off-by: Vineet Gupta

ARC: [plat-eznps] Use dedicated identity auxiliary register.

2016-05-09T04:02:33+00:00

With generic "identity" num of CPUs is limited to 256 (8 bit). We use our alternative AUX register GLOBAL_ID (12 bit). Now we can support up to 4096 CPUs. Signed-off-by: Noam Camus

ARC: Fix misspellings in comments.

2016-03-11T09:29:53+00:00

Signed-off-by: Adam Buchbinder Signed-off-by: Vineet Gupta

ARC: [arcompact] entry.S: Improve early return from exception

2015-10-17T12:18:22+00:00

The requirement is to - Reenable Exceptions (AE cleared) - Reenable Interrupts (E1/E2 set) We need to do wiggle these bits into ERSTATUS and call RTIE. Prev version used the pre-exception STATUS32 as starting point for what goes into ERSTATUS. This required explicit fixups of U/DE/L bits. Instead, use the current (in-exception) STATUS32 as starting point. Being in exception handler U/DE/L can be safely assumed to be correct. Only AE/E1/E2 need to be fixed. So the new implementation is slightly better -Avoids read form memory -Is 4 bytes smaller for the typical 1 level of intr configuration -Depicts the semantics more clearly Signed-off-by: Vineet Gupta

ARC: intc: split into ARCompact ISA specific, common bits

2015-06-19T12:39:40+00:00

Signed-off-by: Vineet Gupta

ARC: entry.S: [arcompact] simplify SWITCH_TO_KERNEL_STK

2015-06-19T12:39:40+00:00

Previously this macro was overloaded with stack switching, saving SP at right slot in pt_regs, saving/setup of r25 and setting SP baseline to where pt_regs->sp is saved (vs. bottom of pt_regs) Now it only does SP switch, and leaves SP pointing to bottom of pt_regs. r25 saving is no longer done here to allow for future reordering of regfile in pt_regs w/o touching this macro Signed-off-by: Vineet Gupta

ARC: entry.S: micro-optimize Trap handler

2015-06-19T12:39:39+00:00

Elide the need to re-read ECR in Trap handler by ensuring that EXCEPTION_PROLOGUE does that at the very end just before returning to Trap handler ARCv2 EXCEPTION_PROLOGUE already did that, so same for ARcompact and the common trap handler adjusted to use cached ECR Signed-off-by: Vineet Gupta

ARC: entry.S: split into ARCompact ISA specific, common bits

2015-06-19T12:39:38+00:00

Signed-off-by: Vineet Gupta