kernel/linux.git/arch/arc/include/asm/entry-arcv2.h, branch linux-7.0.y

ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper

2023-12-09T00:30:24+00:00

And for ARcompact variant replace the PUSH/POP macros with gas provided push/pop pseudo-instructions This allows ISA specific implementation e.g. Current ARCv2 PUSH/POP could be replaced with STD/LDL to save 2 registers at a time (w/o bothering with SP update each time) or perhaps use ENTER_S/LEAVE_S to reduce code size For ARCv3 ABI changed so callee regs are now r14-r26 (vs. r13-r25) thus would need a different implementation. Signed-off-by: Vineet Gupta

ARCv2: entry: rearrange pt_regs slightly

2023-08-18T17:30:47+00:00

Instead of r26,fp,sp,r12,r30 order as fp,r30,r12,r26,sp - keeps SP at well known position (right abive hardware autosave) - r26,r12 saved specifically for ARCv2 (and not in ARCv3) kept closer for easy ifdef'ry later Signed-off-by: Vineet Gupta

ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne

2023-08-18T17:30:47+00:00

ARCv2 current ------------ 000007e0 : 7e0: 2482 3c01 sub sp,sp,112 7e4: 1c28 3006 std r0r1,[sp,40] 7e8: 1c30 3086 std r2r3,[sp,48] 7ec: 1c38 3106 std r4r5,[sp,56] 7f0: 1c40 3186 std r6r7,[sp,64] 7f4: 1c48 3206 std r8r9,[sp,72] 7f8: 1c50 3286 std r10r11,[sp,80] 7fc: 1c58 37c0 st blink,[sp,88] 800: 1c0c 36c0 st fp,[sp,12] 804: 1c18 3680 st gp,[sp,24] 808: 1c10 3780 st r30,[sp,16] 80c: 1c14 3300 st r12,[sp,20] 810: 226a 1340 lr r10,[aux_user_sp] 814: 22ca 1702 mov.ne r10,sp 818: 22c0 1f82 0000 0070 add.ne r10,r10,0x70 ^^^^^^^^^ With fix -------- 000007b4 : 7b4: 2482 3c01 sub sp,sp,112 7b8: 1c28 3006 std r0r1,[sp,40] 7bc: 1c30 3086 std r2r3,[sp,48] 7c0: 1c38 3106 std r4r5,[sp,56] 7c4: 1c40 3186 std r6r7,[sp,64] 7c8: 1c48 3206 std r8r9,[sp,72] 7cc: 1c50 3286 std r10r11,[sp,80] 7d0: 1c58 37c0 st blink,[sp,88] 7d4: 1c0c 36c0 st fp,[sp,12] 7d8: 1c18 3680 st gp,[sp,24] 7dc: 1c10 3780 st r30,[sp,16] 7e0: 1c14 3300 st r12,[sp,20] 7e4: 226a 1340 lr r10,[aux_user_sp] 7e8: 22ca 1702 mov.ne r10,sp 7ec: 22d5 1722 add2.ne r10,r10,0x1c Signed-off-by: Vineet Gupta

ARC: entry: replace 8 byte OR with 4 byte BSET

2023-08-18T17:30:47+00:00

FAKE_RET_FROM_EXCEPTION drops down to pure kernel mode. It currently has an 8 byte instruction which can be replaced with 4 byte BSET This is applicable to both ARCv2 and ARCv3 entr code. ARCv2 current ------------ 00000804 : ... 874: 216a 1280 lr r9,[status32] 878: 2146 1809 bic r9,r9,0x20 87c: 2105 1f89 8000 0000 or r9,r9,0x80000000 ^^^^^^^^^ 884: 2029 8240 kflag r9 ARCv2 after ---------- 000007e0 : ... 850: 216a 1280 lr r9,[status32] 854: 2150 1149 bclr r9,r9,0x5 858: 214f 17c9 bset r9,r9,0x1f 85c: 2029 8240 kflag r9 Signed-off-by: Vineet Gupta

ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

2023-08-18T17:30:07+00:00

THe high level structure of most ARC exception handlers is 1. save regfile with EXCEPTION_PROLOGUE 2. setup r0: EFA (not part of pt_regs) 3. setup r1: pointer to pt_regs (SP) 4. drop down to pure kernel mode (from exception) 5. call the Linux "C" handler Remove the boiler plate code by moving #2, #3, #4 into #1. The exceptions to most exceptions are syscall Trap and Machine check which don't do some of above for various reasons, so call a newly introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original EXCEPTION_PROLOGUE) Tested-by: Pavel Kozlov Signed-off-by: Vineet Gupta

ARC: entry: rework (non-functional)

2023-08-18T03:31:59+00:00

- comments update - rename syscall_trace_entry - use PT_xxx in entry code Signed-off-by: Vineet Gupta

ARC: entry: use gp to cache task pointer (vs. r25)

2023-08-18T03:31:59+00:00

The motivation is eventual ABI considerations for ARCv3 but even without it this change us worthwhile as diffstat reduces 100 net lines r25 is a callee saved register, normally not saved by entry code in pt_regs. However because of its usage in CONFIG_ARC_CURR_IN_REG it needs to be. This in turn requires a whole bunch of special casing when we need to access r25. Then there is distinction between user mode r25 vs. kernel mode r25 - hence distinct SAVE_CALLEE_SAVED_{USER,KERNEL} Instead use gp which is a scratch register and thus saved already in entry code. This cleans things up significantly and much nocer on eyes: - SAVE_CALLEE_SAVED_{USER,KERNEL} are now exactly same - no special user_r25 slot in pt_reggs Note that typical global asm registers are callee-saved (r25), but gp is not callee-saved thus needs additional -ffixed- toggle Signed-off-by: Vineet Gupta

ARC: entry: comment

2020-04-13T05:45:35+00:00

Signed-off-by: Vineet Gupta

ARC: add support for DSP-enabled userspace applications

2020-03-16T17:30:49+00:00

To be able to run DSP-enabled userspace applications we need to save and restore following DSP-related registers: At IRQ/exception entry/exit: * DSP_CTRL (save it and reset to value suitable for kernel) * ACC0_LO, ACC0_HI (we already save them as r58, r59 pair) At context switch: * ACC0_GLO, ACC0_GHI * DSP_BFLY0, DSP_FFT_CTRL Reviewed-by: Vineet Gupta Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta

ARC: handle DSP presence in HW

2020-03-16T17:23:44+00:00

When DSP extensions are present, some of the regular integer instructions such as DIV, MACD etc are executed in the DSP unit with semantics alterable by flags in DSP_CTRL aux register. This register is writable by userspace and thus can potentially affect corresponding instructions in kernel code, intentionally or otherwise. So safegaurd kernel by effectively disabling DSP_CTRL upon bootup and every entry to kernel. Do note that for this config we simply zero out the DSP_CTRL reg assuming userspace doesn't really care about DSP. The next patch caters to the DSP aware userspace where this reg is saved/restored upon kernel entry/exit. Reviewed-by: Vineet Gupta Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta