kernel/linux.git/arch/arc/include/asm/cmpxchg.h, branch linux-4.16.y

ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg

2016-05-09T04:02:33+00:00

We need our own implementaions since we lack LLSC support. Our extended ISA provided with optimized solution for all 32bit operations we see in these three headers. Signed-off-by: Noam Camus

ARC: Fix misspellings in comments.

2016-03-11T09:29:53+00:00

Signed-off-by: Adam Buchbinder Signed-off-by: Vineet Gupta

ARC: add/fix some comments in code - no functional change

2015-08-20T13:35:49+00:00

Signed-off-by: Vineet Gupta

ARC: add smp barriers around atomics per Documentation/atomic_ops.txt

2015-06-25T00:30:16+00:00

- arch_spin_lock/unlock were lacking the ACQUIRE/RELEASE barriers Since ARCv2 only provides load/load, store/store and all/all, we need the full barrier - LLOCK/SCOND based atomics, bitops, cmpxchg, which return modified values were lacking the explicit smp barriers. - Non LLOCK/SCOND varaints don't need the explicit barriers since that is implicity provided by the spin locks used to implement the critical section (the spin lock barriers in turn are also fixed in this commit as explained above Cc: Paul E. McKenney Cc: stable@vger.kernel.org Acked-by: Peter Zijlstra (Intel) Signed-off-by: Vineet Gupta

ARC: add compiler barrier to LLSC based cmpxchg

2015-06-25T00:29:23+00:00

When auditing cmpxchg call sites, Chuck noted that gcc was optimizing away some of the desired LDs. | do { | new = old = *ipi_data_ptr; | new |= 1U << msg; | } while (cmpxchg(ipi_data_ptr, old, new) != old); was generating to below | 8015cef8: ld r2,[r4,0] <-- First LD | 8015cefc: bset r1,r2,r1 | | 8015cf00: llock r3,[r4] <-- atomic op | 8015cf04: brne r3,r2,8015cf10 | 8015cf08: scond r1,[r4] | 8015cf0c: bnz 8015cf00 | | 8015cf10: brne r3,r2,8015cf00 <-- Branch doesn't go to orig LD Although this was fixed by adding a ACCESS_ONCE in this call site, it seems safer (for now at least) to add compiler barrier to LLSC based cmpxchg Reported-by: Chuck Jordan Cc: Acked-by: Peter Zijlstra (Intel) Signed-off-by: Vineet Gupta

ARC: Atomic/bitops/cmpxchg/barriers

2013-02-11T14:30:30+00:00

This covers the UP / SMP (with no hardware assist for atomic r-m-w) as well as ARC700 LLOCK/SCOND insns based. Signed-off-by: Vineet Gupta