kernel/linux.git/Documentation/spi, branch v7.0-rc7

Merge tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

2026-02-11T17:43:43+00:00

Pull spi updates from Mark Brown: "The highlight here is that David Lechner has added support for multi-lane SPI devices. Unlike the existing dual/quad SPI support this is for devices (typically ADCs/DACs) which support multiple independent data streams over multiple data lanes, instead of sending one data stream N times as fast they simultaneously transfer N different data streams. This is very similar to the case where multiple devices are grouped together but in this case it's a single device in a way that's visible to software. Otherwise there's been quite a bit of work on existing drivers, both cleanup and feature improvement, and a reasonable collection of new drivers. - Support for multi-lane SPI devices - Preparatory work for some memory mapped flash improvements that will happen in the MTD subsystem - Several conversions to fwnode APIs - A bunch of cleanup and hardening work on the ST drivers - Support for DMA mode on Renesas RZV2H and i.MX target mode - Support for ATCSPI200, AXIADO AX300, NXP XPI and Renesas RZ/N1" * tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (108 commits) spi: tools: Add include folder to .gitignore spi: cadence-qspi: Add support for the Renesas RZ/N1 controller spi: cadence-qspi: Kill cqspi_jh7110_clk_init spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list spi: geni-qcom: Add target abort support spi: geni-qcom: Drop unused msg parameter from timeout handlers spi: geni-qcom: Fix abort sequence execution for serial engine errors spi: geni-qcom: Improve target mode allocation by using proper allocation functions spi: xilinx: use device property accessors. dt-bindings: spi: Add binding for Faraday FTSSP010 spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE spi: dt-bindings: adi,axi-spi-engine: add multi-lane support spi: Documentation: add page on multi-lane support spi: add multi_lane_mode field to struct spi_transfer spi: support controllers with multiple data lanes spi: dt-bindings: add spi-{tx,rx}-lane-map properties spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays spi: dw: Remove not-going-to-be-supported code for Baikal SoC spi: cadence-qspi: Use a default value for cdns,fifo-width spi: cadence-qspi: Make sure write protection is disabled ...

spi: Documentation: add page on multi-lane support

2026-02-02T12:12:45+00:00

Add a new page to Documentation/spi/ describing how multi-lane SPI support works. This is uncommon functionality so it deserves its own documentation page. Reviewed-by: Marcelo Schmitt Signed-off-by: David Lechner Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-5-12af183c06eb@baylibre.com Signed-off-by: Mark Brown

Documentation: use a source-read extension for the index link boilerplate

2026-01-23T18:59:34+00:00

The root document usually has a special :ref:`genindex` link to the generated index. This is also the case for Documentation/index.rst. The other index.rst files deeper in the directory hierarchy usually don't. For SPHINXDIRS builds, the root document isn't Documentation/index.rst, but some other index.rst in the hierarchy. Currently they have a ".. only::" block to add the index link when doing SPHINXDIRS html builds. This is obviously very tedious and repetitive. The link is also added to all index.rst files in the hierarchy for SPHINXDIRS builds, not just the root document. Put the boilerplate in a sphinx-includes/subproject-index.rst file, and include it at the end of the root document for subproject builds in an ad-hoc source-read extension defined in conf.py. For now, keep having the boilerplate in translations, because this approach currently doesn't cover translated index link headers. Cc: Jonathan Corbet Cc: Mauro Carvalho Chehab Cc: Randy Dunlap Signed-off-by: Jani Nikula Tested-by: Mauro Carvalho Chehab Reviewed-by: Mauro Carvalho Chehab [jc: did s/doctree/kern_doc_dir/ ] Signed-off-by: Jonathan Corbet Message-ID: <20260123143149.2024303-1-jani.nikula@intel.com>

spi: Enable controllers to extend the SPI protocol with MOSI idle configuration

2024-07-29T00:19:51+00:00

The behavior of an SPI controller data output line (SDO or MOSI or COPI (Controller Output Peripheral Input) for disambiguation) is usually not specified when the controller is not clocking out data on SCLK edges. However, there do exist SPI peripherals that require specific MOSI line state when data is not being clocked out of the controller. Conventional SPI controllers may set the MOSI line on SCLK edges then bring it low when no data is going out or leave the line the state of the last transfer bit. More elaborated controllers are capable to set the MOSI idle state according to different configurable levels and thus are more suitable for interfacing with demanding peripherals. Add SPI mode bits to allow peripherals to request explicit MOSI idle state when needed. When supporting a particular MOSI idle configuration, the data output line state is expected to remain at the configured level when the controller is not clocking out data. When a device that needs a specific MOSI idle state is identified, its driver should request the MOSI idle configuration by setting the proper SPI mode bit. Acked-by: Nuno Sa Reviewed-by: Jonathan Cameron Reviewed-by: David Lechner Tested-by: David Lechner Signed-off-by: Marcelo Schmitt Link: https://patch.msgid.link/9802160b5e5baed7f83ee43ac819cb757a19be55.1720810545.git.marcelo.schmitt@analog.com Signed-off-by: Mark Brown

spi: pxa2xx: Drop the stale entry in documentation TOC

2024-05-07T14:53:21+00:00

The documentation had been removed, so should TOC entry. Reported-by: Stephen Rothwell Fixes: 2d069c11e822 ("spi: pxa2xx: Remove outdated documentation") Signed-off-by: Andy Shevchenko Closes: https://lore.kernel.org/r/20240507163131.183813ee@canb.auug.org.au Link: https://lore.kernel.org/r/20240507132002.71938-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown

spi: pxa2xx: Remove outdated documentation

2024-05-03T02:11:34+00:00

The documentation is referring to the legacy enumeration of the SPI host controllers and target devices. It has nothing to do with the modern way, which is the only supported in kernel right now. Hence, remove outdated documentation file. Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20240417110334.2671228-5-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown

spi: docs: drop driver owner initialization

2024-04-02T14:55:35+00:00

Core in spi_register_driver() already sets the .owner, so driver does not need to. Signed-off-by: Krzysztof Kozlowski Link: https://msgid.link/r/20240328203927.156184-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown

spi: pxa2xx: Clean up linux/spi/pxa2xx_spi.h

2024-03-26T11:46:40+00:00

Merge series from Andy Shevchenko : A couple of cleanups against linux/spi/pxa2xx_spi.h. I'm sending this as v3 to land in the SPI subsystem. Meanwhile I'm preparing an update to make linux/spi/pxa2xx_spi.h private to the subsystem (PXA2xx driver). But the second part will be presented later on (likely after v6.9-rc1). That said, this can be routed either via SoC tree or SPI, up to respective maintainers.

spi: remove struct spi_message::is_dma_mapped

2024-03-25T20:30:07+00:00

There are no more users of the deprecated is_dma_mapped in struct spi_message so it can be removed. References in documentation and comments are also removed. A few similar checks if xfer->tx_dma or xfer->rx_dma are not NULL are also removed since these are now guaranteed to be NULL because they were previously set only if is_dma_mapped was true. Signed-off-by: David Lechner Link: https://msgid.link/r/20240325-spi-remove-is_dma_mapped-v2-1-d08d62b61f1c@baylibre.com Signed-off-by: Mark Brown

spi: pxa2xx: Make num_chipselect 8-bit in the struct pxa2xx_spi_controller

2024-03-25T00:49:16+00:00

There is no use for whole 16-bit for the number of chip select pins. Drop it to 8 bits. Acked-by: Arnd Bergmann Signed-off-by: Andy Shevchenko Link: https://msgid.link/r/20240307195056.4059864-3-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown