kernel/linux.git/Documentation/gpu/i915.rst, branch linux-7.1.y

drm/i915: Remove todo and comments about struct_mutex

2025-09-09T14:39:39+00:00

This patch completes the removal of struct_mutex from the driver. Remove the related TODO item, as the transition away from struct_mutex is now complete. Also clean up references to struct_mutex in i915.rst to avoid outdated documentation. Signed-off-by: Luiz Otavio Mello Reviewed-by: Rodrigo Vivi Link: https://lore.kernel.org/r/20250908131518.36625-10-luiz.mello@estudante.ufscar.br Acked-by: Thomas Zimmermann Signed-off-by: Rodrigo Vivi

drm/i915/flipq: Provide the nuts and bolts code for flip queue

2025-06-27T12:54:43+00:00

Provide the lower level code for PIPEDMC based flip queue. We'll use the so called semi-full flip queue mode where the PIPEDMC will start the provided DSB on a scanline a little ahead of the vblank. We need to program the triggering scanline early enough so that the DSB has enough time to complete writing all the double buffered registers before they get latched (at start of vblank). The firmware implements several queues: - 3 "plane queues" which execute a single DSB per entry - 1 "general queue" which can apparently execute 2 DSBs per entry - 1 vestigial "fast queue" that replaced the "simple flip queue" on ADL+, but this isn't supposed to be used due to issues. But we only need a single plane queue really, and we won't actually use it as a real queue because we don't allow queueing multiple commits ahead of time. So the whole thing is perhaps useless. I suppose there migth be some power saving benefits if we would get the flip scheduled by userspace early and then could keep some hardware powered off a bit longer until the DMC kicks off the flipq programming. But that is pure speculation at this time and needs to be proven. The code to hook up the flip queue into the actual atomic commit path will follow later. TODO: need to think how to do the "wait for DMC firmware load" nicely need to think about VRR and PSR etc. v2: Don't write DMC_FQ_W2_PTS_CFG_SEL on pre-lnl Don't oops at flipq init if there is no dmc v3: Adapt to PTL+ flipq changes (different queue entry layout, different trigger event, need VRR TG) Use the actual CDCLK frequency Ask the DSB code how long things are expected to take v3: Adjust the cdclk rounding (docs are 100% vague, Windows rounds like this) Initialize some undocumented magic DMC variables on PTL v4: Use PIPEDMC_FQ_STATUS for busy check (the busy bit in PIPEDMC_FQ_CTRL is apparently gone on LNL+) Based the preempt timeout on the max exec time Preempt before disabling the flip queue Order the PIPEDMC_SCANLINECMP* writes a bit more carefully Fix some typos v5: Try to deal with some clang-20 div-by-zero false positive (Nathan) Add some docs (Jani) Cc: Nathan Chancellor Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä epr Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-5-ville.syrjala@linux.intel.com

drm/i915/plane: rename intel_atomic_plane.[ch] to intel_plane.[ch]

2025-06-19T09:14:29+00:00

It's all atomic, no need to emphasize this. v2: Also update Documentation/gpu/i915.rst (Gustavo) Reviewed-by: Gustavo Sousa Link: https://lore.kernel.org/r/ba5f304e9fe71723191d872e6828d461e1a572bd.1750147992.git.jani.nikula@intel.com Signed-off-by: Jani Nikula

drm/i915: Fix irq related documentation

2024-10-17T21:17:29+00:00

Also update the function names in the documentation. Closes: https://lore.kernel.org/intel-gfx/20241001134331.7b4d4ca5@canb.auug.org.au/ Reported-by: Stephen Rothwell Fixes: 3de5774cb8c0 ("drm/i915/irq: Rename suspend/resume functions") Cc: Jonathan Cavitt Cc: Andi Shyti Reviewed-by: Jonathan Cavitt Reviewed-by: Krzysztof Karas Reviewed-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20241011214111.98128-1-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi

drm: move i915_component.h under include/drm/intel

2024-05-31T13:11:00+00:00

Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also change Documentation/gpu/i915.rst (Andi) Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Tomas Winkler Cc: Jaroslav Kysela Cc: Takashi Iwai Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/a8c07233a8234858eb6711140482ef8db4c91cf4.1717075103.git.jani.nikula@intel.com

Documentation/i915: remove kernel-doc for DMC wakelocks

2024-05-14T12:13:31+00:00

The function descriptions are optional and have not yet been added to the DMC wakelock code, so we shouldn't try to use it. Since this is a regression, remove the kernel-doc entry for DMC wakelocks for now. The proper documentation will be added in a future patch. Fixes: 765425f598c2 ("drm/i915/display: add support for DMC wakelocks") Signed-off-by: Luca Coelho Reviewed-by: Jani Nikula Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240510090502.667556-1-luciano.coelho@intel.com

drm/i915/display: add support for DMC wakelocks

2024-04-17T08:41:08+00:00

In order to reduce the DC5->DC2 restore time, wakelocks have been introduced in DMC so the driver can tell it when registers and other memory areas are going to be accessed and keep their respective blocks awake. Implement this in the driver by adding the concept of DMC wakelocks. When the driver needs to access memory which lies inside pre-defined ranges, it will tell DMC to set the wakelock, access the memory, then wait for a while and clear the wakelock. The wakelock state is protected in the driver with spinlocks to prevent concurrency issues. BSpec: 71583 Signed-off-by: Luca Coelho Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240412094148.808179-2-luciano.coelho@intel.com Signed-off-by: Jani Nikula

drm/i915: Add missing GSCCS documentation

2023-10-02T16:22:44+00:00

Introduce the basic documentation about GSC CS. This "GPU Basics" section is focused on explaining the hardware rather than the driver/uapi, so let's make sure GSC is also properly documented here. v2: Fixes from Matt: typos and acronym. Fixes: 5fd974d164b4 ("drm/i915/mtl: add initial definitions for GSC CS") Suggested-by: Matt Roper Cc: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20230926175554.25968-1-rodrigo.vivi@intel.com

drm/i915: Add missing CCS documentation

2023-10-02T16:22:09+00:00

Let's introduce the basic documentation about CCS. While doing that, also removed the legacy execution flag name. That flag simply doesn't exist for CCS and it is not needed on current context submission. Those flag names are only needed on legacy context, while on new ones we only need to pass the engine ID. It is worth mention that this documentation should probably live with the engine definitions rather than in the i915.rst file directly and that more updates are likely need in this section. But this should come later. v2: Overall improvements from Matt and Tvrtko. Fixes: 944823c94639 ("drm/i915/xehp: Define compute class and engine") Cc: Matt Roper Cc: Sushma Venkatesh Reddy Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Acked-by: Tvrtko Ursulin Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20230926165107.23440-1-rodrigo.vivi@intel.com

Documentation: Fix typos

2023-08-18T17:29:03+00:00

Fix typos in Documentation. Signed-off-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20230814212822.193684-4-helgaas@kernel.org Signed-off-by: Jonathan Corbet