kernel/linux.git/Documentation/driver-api/cxl/linux, branch v6.19.11Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.112025-06-30T23:36:06+00:00Documentation: fix typo in CXL driver documentation2025-06-30T23:36:06+00:00Nai-Chen Chengbleach1827@gmail.com2025-06-10T17:31:52+00:00urn:sha1:7d14230db8a76c776985d510b9f27f66aedc7b14
Fix typo 'enumates' to 'enumerate' in CXL driver operation
documentation to improve readability.
Signed-off-by: Nai-Chen Cheng <bleach1827@gmail.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250610173152.33566-1-bleach1827@gmail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: doc/linux/access-coordinates Update access coordinates calculation methods2025-05-15T23:39:13+00:00Dave Jiangdave.jiang@intel.com2025-05-15T00:09:23+00:00urn:sha1:fc78561595e2fc6ceb8da56b083847227ba9320e
Add documentation on how to calculate the access coordinates for a given
CXL region in detail.
Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-4-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: Sync up the driver-api/cxl documentation2025-05-13T22:12:15+00:00Alison Schofieldalison.schofield@intel.com2025-05-13T21:58:09+00:00urn:sha1:d542461211543522daecb34b7972d8ac1044bc97
pmem.c regs.c mbox.c identifiers were missing. Add them to
memory-devices.rst following their respective DOC comment includes.
Two acpi.c identifiers were available, but not used in kernel-doc's:
1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx
complaint on the ascii art by escaping it.
2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst.
core/features.c is new. Add a "DOC: cxl features" comment to the
source and identifiers to memory_devices.rst.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs - add self-referencing cross-links2025-05-13T20:07:46+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:34+00:00urn:sha1:dba600d0f2e9d2dea53891d95f1ff38d3e089275
Add some crosslinks between pages in the CXL docs - mostly to the
ACPI tables.
Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/linux/memory-hotplug2025-05-13T20:07:45+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:29+00:00urn:sha1:641fdea6b90ee5bd0bab883c767abac69c5389b5
Add documentation on how the CXL driver surfaces memory through the
DAX driver and memory-hotplug.
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-13-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/linux/dax-driver documentation2025-05-13T20:07:45+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:28+00:00urn:sha1:36e9f71bd6fc0f7521c3f05bb57d3db1d821a11f
Add documentation on how the CXL driver interacts with the DAX driver.
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-12-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/linux/cxl-driver - add example configurations2025-05-13T20:07:45+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:27+00:00urn:sha1:ef3a43a69133a211118b5716615cd649ac73b8dc
Add 4 example configurations:
- single device
- cross-host-bridge interleave
- intra-host-bridge-interleave
- multi-level interleave
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-11-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/linux - add cxl-driver theory of operation2025-05-13T20:07:45+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:26+00:00urn:sha1:2e2865a1d0c56987d1eb328645911718f0e672da
Add docs for the CXL driver that explains the base devices,
decoder types, region types, mailbox interfaces, and decoder
programming.
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-10-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/linux - early boot configuration2025-05-13T20:07:45+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:25+00:00urn:sha1:bef826ead3cde244b1a7393bd0c7eee7bbbec8cf
Document __init time configurations that affect CXL driver probe
process and memory region configuration.
Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512162134.3596150-9-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/linux - overview2025-05-13T20:07:45+00:00Gregory Pricegourry@gourry.net2025-05-12T16:21:24+00:00urn:sha1:9bd8546e59542657a7c5a4ee02ea67d3e68f964a
Add type-3 device configuration overview that explains the probe
process for a type-3 device from early-boot through memory-hotplug.
Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512162134.3596150-8-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>