kernel/linux.git/Documentation/devicetree/bindings/timer, branch v6.1.168

Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2022-10-14T18:21:11+00:00

Pull more RISC-V updates from Palmer Dabbelt: - DT updates for the PolarFire SOC - a fix to correct the handling of write-only mappings - m{vetndor,arcd,imp}id is now in /proc/cpuinfo - the SiFive L2 cache controller support has been refactored to also support L3 caches - misc fixes, cleanups and improvements throughout the tree * tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) MAINTAINERS: add RISC-V's patchwork RISC-V: Make port I/O string accessors actually work riscv: enable software resend of irqs RISC-V: Re-enable counter access from userspace riscv: vdso: fix NULL deference in vdso_join_timens() when vfork riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing riscv: Pass -mno-relax only on lld < 15.0.0 RISC-V: Avoid dereferening NULL regs in die() dt-bindings: riscv: add new riscv,isa strings for emulators ...

dt-bindings: timer: sifive,clint: add legacy riscv compatible

2022-10-13T00:05:15+00:00

While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220823183319.3314940-2-mail@conchuod.ie Signed-off-by: Palmer Dabbelt

Merge tag 'devicetree-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2022-10-10T20:13:51+00:00

Pull devicetree updates from Rob Herring: "DT core: - Fix node refcounting in of_find_last_cache_level() - Constify device_node in of_device_compatible_match() - Fix 'dma-ranges' handling in bus controller nodes - Fix handling of initrd start > end - Improve error reporting in of_irq_init() - Taint kernel on DT unittest running - Use strscpy instead of strlcpy - Add a build target, dt_compatible_check, to check for compatible strings used in kernel sources against compatible strings in DT schemas. - Handle DT_SCHEMA_FILES changes when rebuilding DT bindings: - LED bindings for MT6370 PMIC - Convert Mediatek mtk-gce mailbox, MIPS CPU interrupt controller, mt7621 I2C, virtio,pci-iommu, nxp,tda998x, QCom fastrpc, qcom,pdc, and arm,versatile-sysreg to DT schema format - Add nvmem cells to u-boot,env schema - Add more LED_COLOR_ID definitions - Require 'opp-table' uses to be a node - Various schema fixes to match QEMU 'virt' DT usage - Tree wide dropping of redundant 'Device Tree Binding' in schema titles - More (unevaluated|additional)Properties fixes in schema child nodes - Drop various redundant minItems equal to maxItems" * tag 'devicetree-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (62 commits) of: base: Shift refcount decrement in of_find_last_cache_level() dt-bindings: leds: Add MediaTek MT6370 flashlight dt-bindings: leds: mt6370: Add MediaTek MT6370 current sink type LED indicator dt-bindings: mailbox: Convert mtk-gce to DT schema of: base: make of_device_compatible_match() accept const device node of: Fix "dma-ranges" handling for bus controllers of: fdt: Remove unused struct fdt_scan_status dt-bindings: display: st,stm32-dsi: Handle data-lanes in DSI port node dt-bindings: timer: Add power-domains for TI timer-dm on K3 dt: Add a check for undocumented compatible strings in kernel kbuild: take into account DT_SCHEMA_FILES changes while checking dtbs dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML dt-bindings: i2c: migrate mt7621 text bindings to YAML dt-bindings: power: gpcv2: correct patternProperties dt-bindings: virtio: Convert virtio,pci-iommu to DT schema dt-bindings: timer: arm,arch_timer: Allow dual compatible string dt-bindings: arm: cpus: Add kryo240 compatible dt-bindings: display: bridge: nxp,tda998x: Convert to json-schema dt-bindings: nvmem: u-boot,env: add basic NVMEM cells dt-bindings: remoteproc: qcom,adsp: enforce smd-edge schema ...

Merge tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2022-10-10T17:16:00+00:00

Pull timer updates from Thomas Gleixner: "A boring time, timekeeping, timers update: - No core code changes - No new clocksource/event driver - Cleanup of the TI DM clocksource/event driver - The usual set of device tree binding updates - Small improvement, fixes and cleanups all over the place" * tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value clocksource/drivers/imx-sysctr: handle nxp,no-divider property dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get() clocksource/drivers/timer-ti-dm: Add flag to detect omap1 clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driver clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errors clocksource/drivers/timer-ti-dm: Move private defines to the driver clocksource/drivers/timer-ti-dm: Simplify register access further clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write() clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read() clocksource/drivers/timer-ti-dm: Drop unused functions clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probe clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921 clocksource/drivers/exynos_mct: Enable building on ARTPEC clocksource/drivers/exynos_mct: Support local-timers property clocksource/drivers/exynos_mct: Support frc-shared property dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support clocksource/drivers/sun4i: Add definition of clear interrupt clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC ...

dt-bindings: timer: Add power-domains for TI timer-dm on K3

2022-09-29T19:02:47+00:00

On K3 SoCs, the power-domains property is needed. On the earlier SoCs, the power-domains property is handled by the interconnect target module parent device. Cc: Daniel Lezcano Cc: Grygorii Strashko Cc: Keerthy Cc: Nishanth Menon Cc: Vignesh Raghavendra Signed-off-by: Tony Lindgren Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220919112357.64997-1-tony@atomide.com Signed-off-by: Rob Herring

dt-bindings: timer: arm,arch_timer: Allow dual compatible string

2022-09-26T18:35:27+00:00

Since the Armv7 and Armv8 architected timers are compatible, it is valid to expose a devicetree node with compatible string "arm,armv8-timer" followed by "arm,armv7-timer". For example a 32-bit guest running on a 64-bit machine may look for the v7 string even though the hardware is v8. VMMs such as QEMU and kvmtool have been using this compatible string for some time. Clean up the compatible list a little and add the dual option. Acked-by: Krzysztof Kozlowski Signed-off-by: Jean-Philippe Brucker Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20220922161149.371565-1-jean-philippe@linaro.org Signed-off-by: Rob Herring

dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property

2022-09-20T08:49:46+00:00

The base clock input to system counter is internally divided by 3 in previous design, but there is change that no divider now. So add a property to indicate that. Signed-off-by: Peng Fan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220902111207.2902493-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano

dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support

2022-09-20T08:49:45+00:00

The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch Link: https://lore.kernel.org/r/20220609112738.359385-2-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano

dt-bindings: timer: Add missing (unevaluated|additional)Properties on child nodes

2022-08-31T20:47:15+00:00

In order to ensure only documented properties are present, node schemas must have unevaluatedProperties or additionalProperties set to false (typically). Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220823145649.3118479-16-robh@kernel.org

dt-bindings: Remove 'Device Tree Bindings' from end of title:

2022-08-25T19:06:57+00:00

As indicated in link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/ DT schema files should not have 'Device Tree Binding' as part of there title: line. Remove this in most .yaml files, so hopefully preventing developers copying it into new .yaml files, and being asked to remove it. Signed-off-by: Andrew Lunn Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch Signed-off-by: Rob Herring