Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v7.0-rc7 2026-02-22T17:43:11+00:00 2026-02-22T17:43:11+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-02-22T17:43:11+00:00 urn:sha1:5f2eac7767493bf23e6552db82ab25de0dccd54f Pull RTC updates from Alexandre Belloni: - loongson: Loongson-2K0300 support - s35390a: nvmem support - zynqmp: rework calibration * tag 'rtc-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: rtc: ds1390: fix number of bytes read from RTC rtc: class: Remove duplicate check for alarm rtc: optee: simplify OP-TEE context match rtc: interface: Alarm race handling should not discard preceding error rtc: s35390a: implement nvmem support rtc: loongson: Add Loongson-2K0300 support dt-bindings: rtc: loongson: Document Loongson-2K0300 compatible dt-bindings: rtc: loongson: Correct Loongson-1C interrupts property dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2N support dt-bindings: rtc: cpcap: convert to schema rtc: zynqmp: use dynamic max and min offset ranges rtc: zynqmp: rework set_offset rtc: zynqmp: rework read_offset rtc: zynqmp: check calibration max value rtc: zynqmp: correct frequency value rtc: amlogic-a4: Remove IRQF_ONESHOT rtc: pcf8563: use correct of_node for output clock rtc: max31335: use correct CONFIG symbol in IS_REACHABLE() rtc: nvvrs: Add ARCH_TEGRA to the NV VRS RTC driver 2026-01-30T23:12:32+00:00 Binbin Zhou zhoubinbin@loongson.cn 2026-01-17T02:26:49+00:00 urn:sha1:5d4899d4859f812290bf2fc458a517781fe6eeca Add "loongson,ls2k0300-rtc" dedicated compatible to represent the RTC interface of the Loongson-2K0300 chip. Its hardware design is similar to that of the Loongson-1B, but it does not support the alarm feature. Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/0c6a4fd221b5bf05f06cae9bb543a5bf7ea59f57.1768616276.git.zhoubinbin@loongson.cn Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2026-01-30T23:12:31+00:00 Binbin Zhou zhoubinbin@loongson.cn 2026-01-17T02:26:48+00:00 urn:sha1:da9934a6583adc40ac0c9cc21e7419617ad985fd The `interrupts` property indicates an RTC alarm interrupt, which is required for RTCs that support the alarm feature, which is not supported by the Loongson-1C RTC. We exclude it for a more accurate description. Changing the `allowed` property is ABI-breaking behavior, but throughout the existing Loongson DTS{i}, the description of the RTC nodes conforms to the modified bingding rules. Thus, the existing Loongson DTS{i} will not be affected. Fixes: 487ef32caebe ("dt-bindings: rtc: Split loongson,ls2x-rtc into SoC-based compatibles") Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/b6295c907410f6708115cba4df0959ee6629f8a5.1768616276.git.zhoubinbin@loongson.cn Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2026-01-30T23:10:26+00:00 Ovidiu Panait ovidiu.panait.rb@renesas.com 2026-01-25T19:27:03+00:00 urn:sha1:f3ac75cfacc66f48523e730646dbbc2f19844799 The Renesas RZ/V2N (r9a09g056) RTC is identical to the RZ/V2H (r9a09g057) variant. Add the compatible string for RZ/V2N and extend the existing RZ/V2H reset configuration to cover both variants. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260125192706.27099-4-ovidiu.panait.rb@renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2026-01-29T15:46:37+00:00 Svyatoslav Ryhel clamor95@gmail.com 2026-01-25T13:42:58+00:00 urn:sha1:96a77ec577d4117f13e2527c9a377d6ba637f5c0 Convert RTC devicetree bindings for the Motorola CPCAP MFD from TXT to YAML format. This patch does not change any functionality; the bindings remain the same. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Link: https://patch.msgid.link/20260125134302.45958-7-clamor95@gmail.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2025-12-16T16:17:59+00:00 Linus Walleij linusw@kernel.org 2025-12-16T09:52:10+00:00 urn:sha1:54de247a0efa4c6176ba6840a58e2fb0b2130e2d My name is stamped into maintainership for a big slew of DT bindings. Now that it is changing, switch it over to my kernel.org mail address, which will hopefully be stable for the rest of my life. Signed-off-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20251216-maintainers-dt-v1-1-0b5ab102c9bb@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org> 2025-12-08T21:41:59+00:00 Sven Peter sven@kernel.org 2025-11-12T11:16:47+00:00 urn:sha1:07049187e83072e187d7a9f3386286e59c83e8ee Apple Silicon Macs (M1, etc.) have an RTC that is part of the PMU IC, but most of the PMU functionality is abstracted out by the SMC. An additional RTC offset stored inside NVMEM is required to compute the current date/time. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Sven Peter <sven@kernel.org> Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Reviewd-by: Mark Kettenis <kettenis@openbsd.org> Link: https://patch.msgid.link/20251112-macsmc-subdevs-v5-1-728e4b91fe81@gmail.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2025-12-08T21:28:17+00:00 Ovidiu Panait ovidiu.panait.rb@renesas.com 2025-11-07T21:07:03+00:00 urn:sha1:4800046b56a5b240ab280f55165484a9dbdf7092 The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S (r9a08g045), with the following differences: - It lacks the time capture functionality - The maximum supported periodic interrupt frequency is 128Hz instead of 256Hz - It requires two reset lines instead of one Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update the binding accordingly: - Allow "resets" to contain one or two entries depending on the SoC. - Add "reset-names" property, but make it required only for RZ/V2H. Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251107210706.45044-2-ovidiu.panait.rb@renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2025-11-06T22:50:07+00:00 Shubhi Garg shgarg@nvidia.com 2025-10-07T13:57:35+00:00 urn:sha1:4c03653f19ae9b57e84cfe2d625b13bd1dfd449e Add device tree bindings for NVIDIA VRS (Voltage Regulator Specification) RTC device. NVIDIA VRS is a Power Management IC (PMIC) that implements a power sequencing solution with I2C interface. The device includes RTC which provides functionality to get/set system time, retain system time across boot, wake system from suspend and shutdown state. Supported platforms: - NVIDIA Jetson AGX Orin Developer Kit - NVIDIA IGX Orin Development Kit - NVIDIA Jetson Orin NX Developer Kit - NVIDIA Jetson Orin Nano Developer Kit Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20251007135738.487694-2-shgarg@nvidia.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 2025-11-06T22:16:13+00:00 CL Wang cl634@andestech.com 2025-09-15T03:14:37+00:00 urn:sha1:e1794c59730a68d6ece55430766cc51720ac653a Document Device Tree bindings for the Andes ATCRTC100 Real-Time Clock. Signed-off-by: CL Wang <cl634@andestech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250915031439.2680364-2-cl634@andestech.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>