kernel/linux.git/Documentation/devicetree/bindings/pinctrl, branch v7.0.10

dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: add missing items keyword

2026-05-23T11:09:08+00:00

[ Upstream commit a92b75100826b1ea27e6b8a678e53970ad4736d7 ] Even though the type of the 'groups' property of a pinmux node is specified as string-array in pinmux-node.yaml, but trying to use multiple strings causes dtbs_check warnings. For example, checking the following dts ... $ cat arch/arm64/boot/dts/marvell/armada-3720-test.dts /dts-v1/; #include "armada-372x.dtsi" &pinctrl_nb { pwm-gpio-pins { groups = "pwm0", "pwm1", "pwm2", "pwm3"; function = "gpio"; }; }; ... results in this warning: arch/arm64/boot/dts/marvell/armada-3720-test.dtb: pinctrl@13800 (marvell,armada3710-nb-pinctrl): pwm-gpio-pins:groups: ['pwm0', 'pwm1', 'pwm2', 'pwm3'] is too long from schema $id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml Add the missing 'items' keyword to the schema to allow using multiple strings without such warnings. Also adjust the indentation of the next statements accordingly. Signed-off-by: Gabor Juhos Acked-by: Conor Dooley Fixes: c1c9641a04e83 ("dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema") Reviewed-by: Miquel Raynal Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

Merge tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2026-02-16T17:35:24+00:00

Pull pin control updates from Linus Walleij: "Core changes: - Drop the unused devm_pinctrl_unregister() function - Move pretended generic pin control functionality out of the core and into the Amlogic AM4 driver. We have something better coming (hopefully) New hardware support: - Spacemit K3 (RISC-V) pin control support - Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support - Exynos9610 (ARM64) pin control support - Qualcomm Mahua TLMM (ARM64) pin control support - Microchip Polarfire MSSIO (RISC-V) pin control support - Ocelot LAN9645XF (multiplatform) pin control support Improvements: - Using a few more guards for locking - Various nonurgent fixes and tweaks" * tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (73 commits) pinctrl: generic: move function to amlogic-am4 driver pinctrl: intel: Align Copyright note with corporate guidelines pinctrl: mediatek: remove unused drv_offset field pinctrl: canaan: k230: Fix NULL pointer dereference when parsing devicetree pinctrl: single: fix refcount leak in pcs_add_gpio_func() pinctrl: meson: amlogic-a4: Fix device node reference leak in bank helpers pinctrl: qcom: sm8250-lpass-lpi: Fix i2s2_data_groups definition pinctrl: core: Remove duplicate error messages pinctrl: core: Simplify devm_pinctrl_*() pinctrl: core: Remove unused devm_pinctrl_unregister() dt-bindings: pinctrl: spacemit: fix drive-strength check warning pinctrl: fix kismet issues with GENERIC_PINCTRL pinctrl: tangier: Join tng_pinctrl_probe() into its wrapper pinctrl: tangier: Remove duplicate error messages pinctrl: lynxpoint: Remove duplicate error messages pinctrl: cherryview: Remove duplicate error messages pinctrl: baytrail: Remove duplicate error messages pinctrl: intel: Remove duplicate error messages pinctrl: equilibrium: Fix device node reference leak in pinbank_init() dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x ...

dt-bindings: pinctrl: spacemit: fix drive-strength check warning

2026-02-03T00:04:51+00:00

The problem is that one value from drive-strength may match to more than two different enum groups which lead to DT complaint, switch to use 'anyOf' to fix this kind warning. Fixes: c3efac0592f8 ("dt-bindings: pinctrl: spacemit: convert drive strength to schema format") Signed-off-by: Yixun Lan Acked-by: Conor Dooley Reported-by: Conor Dooley Signed-off-by: Linus Walleij

dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: fix 'usb32_drvvbus0' group name

2026-01-27T09:49:36+00:00

The trailing '0' character of the 'usb32_drvvbus0' pin group got removed during converting the bindings to DT schema. $ git grep -n usb32_drvvbus v6.18 v6.18:Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt:106:group usb32_drvvbus0 v6.18:drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:195: PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), $ git grep -n usb32_drvvbus v6.19-rc1 v6.19-rc1:Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml:91: usb2_drvvbus1, usb32_drvvbus ] v6.19-rc1:drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:195: PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), Add it back to match the group name with the one the driver expects. Fixes: c1c9641a04e8 ("dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema") Signed-off-by: Gabor Juhos Acked-by: Conor Dooley Reviewed-by: Miquel Raynal Signed-off-by: Linus Walleij

dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x

2026-01-27T09:31:52+00:00

Document LAN969x compatibles for SGPIO. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Linus Walleij

dt-bindings: pinctrl: ocelot: Add LAN9645x SoC support

2026-01-27T09:04:09+00:00

Add documentation for the compatibles designated for the following SKUs in the LAN9645x family: lan96455f lan96457f lan96459f with fallback a compatible for the smallest 5-ported SKUs lan96455f. Reviewed-by: Steen Hegelund Reviewed-by: Daniel Machon Signed-off-by: Jens Emil Schulz Østergaard Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij

dt-bindings: pinctrl: document polarfire soc mssio pin controller

2026-01-21T12:13:37+00:00

On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6, which determine what function in routed to them, and MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin. Document it, including several custom configuration options that stem from MSS Configurator options (the MSS Configurator is part of the FPGA tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping with an MSS Configurator option, unlike clamp-diode or lockdown, and I do not know the effect of any bits in the field. I have no been able to find an explanation for these bits in documentation. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij

dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block

2026-01-21T12:11:56+00:00

Document the pinctrl compatible for the Mahua SoC, a 12-core variant of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt for GPIO 155 instead of GPIO 143 as seen on Glymur. Signed-off-by: Gopikrishna Garmidi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij

dt-bindings: pinctrl: spacemit: add syscon property

2026-01-19T23:50:18+00:00

In order to access the protected IO power domain registers, a valid unlock sequence must be performed by writing the required keys to the AIB Secure Access Register (ASAR). The ASAR register resides within the APBC register address space. A corresponding syscon property is added to allow the pinctrl driver to access this register. Signed-off-by: Troy Mitchell Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij

Merge tag 'samsung-pinctrl-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

2026-01-18T23:45:43+00:00

Samsung pinctrl drivers changes for v6.20 Add new pin controllers for Samsung Exynos9610 SoC. Signed-off-by: Linus Walleij