kernel/linux.git/Documentation/devicetree/bindings/net/dsa, branch v5.16

dt-bindings: net: dsa: sja1105: add {rx,tx}-internal-delay-ps

2021-10-20T10:32:28+00:00

Add a schema validator to nxp,sja1105.yaml and to dsa.yaml for explicit MAC-level RGMII delays. These properties must be per port and must be present only for a phy-mode that represents RGMII. We tell dsa.yaml that these port properties might be present, we also define their valid values for SJA1105. We create a common definition for the RX and TX valid range, since it's quite a mouthful. We also modify the example to include the explicit RGMII delay properties. On the fixed-link ports (in the example, port 4), having these explicit delays is actually mandatory, since with the new behavior, the driver shouts that it is interpreting what delays to apply based on phy-mode. Signed-off-by: Vladimir Oltean Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

dt-bindings: net: dsa: inherit the ethernet-controller DT schema

2021-10-20T10:32:28+00:00

Since a switch is basically a bunch of Ethernet controllers, just inherit the common schema for one to get stronger type validation of the properties of a port. For example, before this change it was valid to have a phy-mode = "xfi" even if "xfi" is not part of ethernet-controller.yaml, now it is not. Signed-off-by: Vladimir Oltean Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

dt-bindings: net: dsa: sja1105: fix example so all ports have a phy-handle of fixed-link

2021-10-20T10:32:28+00:00

All ports require either a phy-handle or a fixed-link, and port 3 in the example didn't have one. Add it. Signed-off-by: Vladimir Oltean Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

dt-bindings: net: dsa: realtek-smi: document new compatible rtl8365mb

2021-10-18T13:02:56+00:00

rtl8365mb is a new realtek-smi subdriver for the RTL8365MB-VC 4+1 port 10/100/1000M Ethernet switch controller. Its compatible string is "realtek,rtl8365mb". Signed-off-by: Alvin Šipraga Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Acked-by: Rob Herring Reviewed-by: Linus Walleij Signed-off-by: David S. Miller

dt-bindings: net: dsa: qca8k: convert to YAML schema

2021-10-15T10:06:38+00:00

Convert the qca8k bindings to YAML format. Signed-off-by: Matthew Hagan Co-developed-by: Ansuel Smith Signed-off-by: Ansuel Smith Signed-off-by: David S. Miller

dt-bindings: net: dsa: qca8k: document support for qca8328

2021-10-15T10:06:38+00:00

QCA8328 is the bigger brother of qca8327. Document the new compatible binding and add some information to understand the various switch compatible. Signed-off-by: Ansuel Smith Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding

2021-10-15T10:06:37+00:00

Document new binding qca,ignore-power-on-sel used to ignore power on strapping and use sw regs instead. Document qca,led-open.drain to set led to open drain mode, the qca,ignore-power-on-sel is mandatory with this enabled or an error will be reported. Signed-off-by: Ansuel Smith Signed-off-by: David S. Miller

dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll

2021-10-15T10:06:37+00:00

Document qca,sgmii-enable-pll binding used in the CPU nodes to enable SGMII PLL on MAC config. Signed-off-by: Ansuel Smith Signed-off-by: David S. Miller

dt-bindings: net: dsa: qca8k: Document support for CPU port 6

2021-10-15T10:06:37+00:00

The switch now support CPU port to be set 6 instead of be hardcoded to 0. Document support for it and describe logic selection. Signed-off-by: Ansuel Smith Signed-off-by: David S. Miller

dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties

2021-10-15T10:06:37+00:00

Add names and descriptions of additional PORT0_PAD_CTRL properties. qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock phase to failling edge. Co-developed-by: Matthew Hagan Signed-off-by: Matthew Hagan Signed-off-by: Ansuel Smith Signed-off-by: David S. Miller