<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/Documentation/devicetree/bindings/iommu, branch linux-7.0.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-01-16T12:41:27+00:00</updated>
<entry>
<title>dt-bindings: iommu: Add NVIDIA Tegra CMDQV support</title>
<updated>2026-01-16T12:41:27+00:00</updated>
<author>
<name>Ashish Mhetre</name>
<email>amhetre@nvidia.com</email>
</author>
<published>2026-01-13T05:49:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8a59954192eba2d9dd2248dcc7b1f458c082eff2'/>
<id>urn:sha1:8a59954192eba2d9dd2248dcc7b1f458c082eff2</id>
<content type='text'>
The Command Queue Virtualization (CMDQV) hardware is part of the
SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
virtualizing the command queue for the SMMU.

Add a new device tree binding document for nvidia,tegra264-cmdqv.

Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
property. This property is a phandle to the CMDQV device node, allowing
the SMMU driver to associate with its corresponding CMDQV instance.
Restrict this property usage to Nvidia Tegra264 only.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Acked-by: Nicolin Chen &lt;nicolinc@nvidia.com&gt;
Signed-off-by: Ashish Mhetre &lt;amhetre@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'iommu-updates-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux</title>
<updated>2025-12-05T02:05:06+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-12-05T02:05:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ce5cfb0fa20dc6454da039612e34325b7b4a8243'/>
<id>urn:sha1:ce5cfb0fa20dc6454da039612e34325b7b4a8243</id>
<content type='text'>
Pull iommu updates from Joerg Roedel:

 - Introduction of the generic IO page-table framework with support for
   Intel and AMD IOMMU formats from Jason.

   This has good potential for unifying more IO page-table
   implementations and making future enhancements more easy. But this
   also needed quite some fixes during development. All known issues
   have been fixed, but my feeling is that there is a higher potential
   than usual that more might be needed.

 - Intel VT-d updates:
    - Use right invalidation hint in qi_desc_iotlb()
    - Reduce the scope of INTEL_IOMMU_FLOPPY_WA

 - ARM-SMMU updates:
    - Qualcomm device-tree binding updates for Kaanapali and Glymur SoCs
      and a new clock for the TBU.
    - Fix error handling if level 1 CD table allocation fails.
    - Permit more than the architectural maximum number of SMRs for
      funky Qualcomm mis-implementations of SMMUv2.

 - Mediatek driver:
    - MT8189 iommu support

 - Move ARM IO-pgtable selftests to kunit

 - Device leak fixes for a couple of drivers

 - Random smaller fixes and improvements

* tag 'iommu-updates-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (81 commits)
  iommupt/vtd: Support mgaw's less than a 4 level walk for first stage
  iommupt/vtd: Allow VT-d to have a larger table top than the vasz requires
  powerpc/pseries/svm: Make mem_encrypt.h self contained
  genpt: Make GENERIC_PT invisible
  iommupt: Avoid a compiler bug with sw_bit
  iommu/arm-smmu-qcom: Enable use of all SMR groups when running bare-metal
  iommupt: Fix unlikely flows in increase_top()
  iommu/amd: Propagate the error code returned by __modify_irte_ga() in modify_irte_ga()
  MAINTAINERS: Update my email address
  iommu/arm-smmu-v3: Fix error check in arm_smmu_alloc_cd_tables
  dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock
  iommu/vt-d: Restore previous domain::aperture_end calculation
  iommu/vt-d: Fix unused invalidation hint in qi_desc_iotlb
  iommu/vt-d: Set INTEL_IOMMU_FLOPPY_WA depend on BLK_DEV_FD
  iommu/tegra: fix device leak on probe_device()
  iommu/sun50i: fix device leak on of_xlate()
  iommu/omap: simplify probe_device() error handling
  iommu/omap: fix device leaks on probe_device()
  iommu/mediatek-v1: add missing larb count sanity check
  iommu/mediatek-v1: fix device leaks on probe()
  ...
</content>
</entry>
<entry>
<title>Merge tag 'devicetree-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux</title>
<updated>2025-12-04T23:50:37+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-12-04T23:50:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6044a1ee9dca906a807ba786421dc4254191ffd5'/>
<id>urn:sha1:6044a1ee9dca906a807ba786421dc4254191ffd5</id>
<content type='text'>
Pull devicetree updates from Rob Herring:
 "DT bindings:

   - Convert lattice,ice40-fpga-mgr, apm,xgene-storm-dma,
     brcm,sr-thermal, amazon,al-thermal, brcm,ocotp, mt8173-mdp, Actions
     Owl SPS, Marvell AP80x System Controller, Marvell CP110 System
     Controller, cznic,moxtet, and apm,xgene-slimpro-mbox to DT schema
     format

   - Add i.MX95 fsl,irqsteer, MT8365 Mali Bifrost GPU, Anvo ANV32C81W
     EEPROM, and Microchip pic64gx PLIC

   - Add missing LGE, AMD Seattle, and APM X-Gene SoC platform
     compatibles

   - Updates to brcm,bcm2836-l1-intc, brcm,bcm2835-hvs, and bcm2711-hdmi
     bindings to fix warnings on BCM2712 platforms

   - Drop obsolete db8500-thermal.txt

   - Treewide clean-up of extra blank lines and inconsistent quoting

   - Ensure all .dtbo targets are applied to a base .dtb

   - Speed up dt_binding_check by skipping running validation on empty
     examples

  DT core:

   - Add of_machine_device_match() and of_machine_get_match_data()
     helpers and convert users treewide

   - Fix bounds checking of address properties in FDT code. Rework the
     code to have a single implementation of the bounds checks.

   - Rework of_irq_init() to ignore any implicit interrupt-parent (i.e.
     in a parent node) on nodes without an interrupt. This matches the
     spec description and fixes some RISC-V platforms.

   - Avoid a spurious message on overlay removal

   - Skip DT kunit tests on RISCV+ACPI"

* tag 'devicetree-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
  dt-bindings: kbuild: Skip validating empty examples
  dt-bindings: interrupt-controller: brcm,bcm2836-l1-intc: Drop interrupt-controller requirement
  dt-bindings: display: Fix brcm,bcm2835-hvs bindings for BCM2712
  dt-bindings: display: bcm2711-hdmi: Add interrupt details for BCM2712
  of: Skip devicetree kunit tests when RISCV+ACPI doesn't populate root node
  soc: tegra: Simplify with of_machine_device_match()
  soc: qcom: ubwc: Simplify with of_machine_get_match_data()
  powercap: dtpm: Simplify with of_machine_get_match_data()
  platform: surface: Simplify with of_machine_get_match_data()
  irqchip/atmel-aic: Simplify with of_machine_get_match_data()
  firmware: qcom: scm: Simplify with of_machine_device_match()
  cpuidle: big_little: Simplify with of_machine_device_match()
  cpufreq: sun50i: Simplify with of_machine_device_match()
  cpufreq: mediatek: Simplify with of_machine_get_match_data()
  cpufreq: dt-platdev: Simplify with of_machine_get_match_data()
  of: Add wrappers to match root node with OF device ID tables
  dt-bindings: eeprom: at25: Add Anvo ANV32C81W
  of/reserved_mem: Simplify the logic of __reserved_mem_alloc_size()
  of/reserved_mem: Simplify the logic of fdt_scan_reserved_mem_reg_nodes()
  of/reserved_mem: Simplify the logic of __reserved_mem_reserve_reg()
  ...
</content>
</entry>
<entry>
<title>Merge branches 'arm/smmu/updates', 'arm/smmu/bindings', 'mediatek', 'nvidia/tegra', 'intel/vt-d', 'amd/amd-vi' and 'core' into next</title>
<updated>2025-11-28T07:44:21+00:00</updated>
<author>
<name>Joerg Roedel</name>
<email>joerg.roedel@amd.com</email>
</author>
<published>2025-11-28T07:44:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0d081b16946ef449fcb35b6edc1ef6f9fea6f0a0'/>
<id>urn:sha1:0d081b16946ef449fcb35b6edc1ef6f9fea6f0a0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock</title>
<updated>2025-11-24T16:55:18+00:00</updated>
<author>
<name>Konrad Dybcio</name>
<email>konrad.dybcio@linaro.org</email>
</author>
<published>2025-11-04T14:47:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fe6262910cd3fefe8a23d5f59a701085f7adad6b'/>
<id>urn:sha1:fe6262910cd3fefe8a23d5f59a701085f7adad6b</id>
<content type='text'>
Some IOMMUs on some platforms (there doesn't seem to be a good denominator
for this) require the presence of a third clock, specifically relating
to the instance's Translation Buffer Unit (TBU).

Stephan Gerhold noted [1] that according to Qualcomm Snapdragon 410E
Processor (APQ8016E) Technical Reference Manual, SMMU chapter, section
"8.8.3.1.2 Clock gating", which reads:

For APPS TCU/TBU (TBU to TCU interface is asynchronous)
Software should turn ON clock to APPS TCU
  - During APPS TCU register programming sequence

For GPU TCU/TBU (TBU to TCU interface is synchronous)
Software should turn ON clock to GPU TBU
  - During GPU TLB invalidation sequence &lt;=====================
Software should turn ON clock to GPU TCU
  - During GPU TCU register programming sequence
  - While GPU master clock is Active

The clock should be turned on at least during TLB invalidation on the
GPU SMMU instance. This is corroborated by Commit 5bc1cf1466f6
("iommu/qcom: add optional 'tbu' clock for TLB invalidate").

This is also not to be confused with qcom,sdm845-tbu, which is a
description of a debug interface, absent on the generation of hardware
that this binding describes.

Allow this clock.

[1] https://lore.kernel.org/linux-arm-msm/aPX_cKtial56AgvU@linaro.org/

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Konrad Dybcio &lt;konrad.dybcio@linaro.org&gt;
Reviewed-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: arm-smmu: Add Kaanapali and Glymur GPU SMMU</title>
<updated>2025-11-18T17:04:13+00:00</updated>
<author>
<name>Akhil P Oommen</name>
<email>akhilpo@oss.qualcomm.com</email>
</author>
<published>2025-11-18T08:50:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3b9b0816f9ed757072dc8b1088ea09b7c69c543d'/>
<id>urn:sha1:3b9b0816f9ed757072dc8b1088ea09b7c69c543d</id>
<content type='text'>
Update the devicetree bindings to document the GPU SMMUs present in
Kaanapali and Glymur chipsets.

Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Akhil P Oommen &lt;akhilpo@oss.qualcomm.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/689028/
Message-ID: &lt;20251118-kaana-gpu-support-v4-19-86eeb8e93fb6@oss.qualcomm.com&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Remove extra blank lines</title>
<updated>2025-11-17T17:24:50+00:00</updated>
<author>
<name>Rob Herring (Arm)</name>
<email>robh@kernel.org</email>
</author>
<published>2025-10-23T14:37:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0b2333183ade2bad21a7ed7b16b93d87d0a83043'/>
<id>urn:sha1:0b2333183ade2bad21a7ed7b16b93d87d0a83043</id>
<content type='text'>
Generally at most 1 blank line is the standard style for DT schema
files. Remove the few cases with more than 1 so that the yamllint check
for this can be enabled.

Acked-by: Lee Jones &lt;lee@kernel.org&gt;
Reviewed-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt; # remoteproc
Acked-by: Georgi Djakov &lt;djakov@kernel.org&gt;
Acked-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Acked-by: Andi Shyti &lt;andi.shyti@kernel.org&gt;
Acked-by: Bartosz Golaszewski &lt;bartosz.golaszewski@linaro.org&gt;
Acked-by: Jonathan Cameron &lt;jonathan.cameron@huawei.com&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Uwe Kleine-König &lt;ukleinek@kernel.org&gt; # for allwinner,sun4i-a10-pwm.yaml
Reviewed-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt; # mtd
Acked-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Acked-by: Mark Brown &lt;broonie@kernel.org&gt;
Acked-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Acked-by: Sebastian Reichel &lt;sebastian.reichel@collabora.com&gt;
Acked-by: Manivannan Sadhasivam &lt;mani@kernel.org&gt; # For PCI controller bindings
Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: arm-smmu: Add compatible for Kaanapali and Glymur SoCs</title>
<updated>2025-11-03T15:55:07+00:00</updated>
<author>
<name>Jingyi Wang</name>
<email>jingyi.wang@oss.qualcomm.com</email>
</author>
<published>2025-10-22T06:15:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=45859c059c208a71eb9d45d3519593ba0a17c5ff'/>
<id>urn:sha1:45859c059c208a71eb9d45d3519593ba0a17c5ff</id>
<content type='text'>
Qualcomm Kaanapali and Glymur SoCs include apps smmu that implements
arm,mmu-500, which is used to translate device-visible virtual addresses
to physical addresses. Add compatible for these items.

Co-developed-by: Pankaj Patil &lt;pankaj.patil@oss.qualcomm.com&gt;
Signed-off-by: Pankaj Patil &lt;pankaj.patil@oss.qualcomm.com&gt;
Signed-off-by: Jingyi Wang &lt;jingyi.wang@oss.qualcomm.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: mediatek: mt8189: Add bindings for MM &amp; APU &amp; INFRA IOMMU</title>
<updated>2025-10-27T12:42:48+00:00</updated>
<author>
<name>Zhengnan Chen</name>
<email>zhengnan.chen@mediatek.com</email>
</author>
<published>2025-10-18T13:26:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=812df545e3e44051d7fd39c057e53ffb56868451'/>
<id>urn:sha1:812df545e3e44051d7fd39c057e53ffb56868451</id>
<content type='text'>
There are three iommu in total, namely MM_IOMMU, APU_IOMMU, INFRA_IOMMU,
Add bindings for them.

Signed-off-by: Zhengnan Chen &lt;zhengnan.chen@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2025-10-02T00:32:51+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-10-02T00:32:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=38057e323657695ec8f814aff0cdd1c7e00d3e9b'/>
<id>urn:sha1:38057e323657695ec8f814aff0cdd1c7e00d3e9b</id>
<content type='text'>
Pull SoC driver updates from Arnd Bergmann:
 "Lots of platform specific updates for Qualcomm SoCs, including a new
  TEE subsystem driver for the Qualcomm QTEE firmware interface.

  Added support for the Apple A11 SoC in drivers that are shared with
  the M1/M2 series, among more updates for those.

  Smaller platform specific driver updates for Renesas, ASpeed,
  Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
  SoCs.

  Driver updates in the cache controller, memory controller and reset
  controller subsystems.

  SCMI firmware updates to add more features and improve robustness.
  This includes support for having multiple SCMI providers in a single
  system.

  TEE subsystem support for protected DMA-bufs, allowing hardware to
  access memory areas that managed by the kernel but remain inaccessible
  from the CPU in EL1/EL0"

* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
  soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
  soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
  soc: fsl: qe: Change GPIO driver to a proper platform driver
  tee: fix register_shm_helper()
  pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
  dt-bindings: spmi: Add Apple A11 and T2 compatible
  serial: qcom-geni: Load UART qup Firmware from linux side
  spi: geni-qcom: Load spi qup Firmware from linux side
  i2c: qcom-geni: Load i2c qup Firmware from linux side
  soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
  soc: qcom: geni-se: Cleanup register defines and update copyright
  dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
  Documentation: tee: Add Qualcomm TEE driver
  tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
  tee: qcom: add primordial object
  tee: add Qualcomm TEE driver
  tee: increase TEE_MAX_ARG_SIZE to 4096
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
  tee: add close_context to TEE driver operation
  ...
</content>
</entry>
</feed>
